公开(公告)号：US06597656B1

公开(公告)日：2003-07-22

申请号：US09317006

申请日：1999-05-24

申请人： Alain Blanc ,  Sylvie Gohl ,  Alain Saurel ,  Bernard Brezzo ,  Jean-Claude Robbe

发明人： Alain Blanc ,  Sylvie Gohl ,  Alain Saurel ,  Bernard Brezzo ,  Jean-Claude Robbe

IPC分类号： H04L122

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/309 ,  H04L49/455 ,  H04L2012/5627 ,  H04L2012/5647

摘要： A switching system having at least two switch fabrics. Each fabric has a switch core and a set of SCAL (Switch Core Access Layer) receive and transmit elements. The switch cores are preferably located in the same physical area but the SCALs may be distributed in different physical areas. Port Adapters distributed at different physical areas are connected to the switch fabrics via a particular SCAL element so that each switch core can receive cells from any port adapter and conversely any port adapter may receive data from either switch core. Control logic assigns a particular switch core to one port adapter for normal operations while reserving the other switch core for use when the first core is out of service. Each switch core has a mask mechanism which uses the value in a mask register to alter a bitmap value which controls the routing process. The mask registers in the two switch cores are loaded with complementary values.

摘要翻译： 一种具有至少两个交换结构的交换系统。 每个结构具有交换机核心和一组SCAL（交换机核心接入层）接收和发送元素。 交换机核心优选地位于相同的物理区域中，但是SCAL可以分布在不同的物理区域中。 分布在不同物理区域的端口适配器通过特定的SCAL元件连接到交换结构，使得每个交换机核心可以从任何端口适配器接收单元，相反，任何端口适配器可以从交换机核心接收数据。 控制逻辑将特定的交换机核心分配给一个端口适配器进行正常操作，同时在第一个核心停止工作时保留另一个交换机内核以供使用。 每个交换机核心都有一个掩码机制，使用掩码寄存器中的值来更改控制路由进程的位图值。 两个交换机核心中的掩码寄存器加载互补值。

公开(公告)号：US06606300B1

公开(公告)日：2003-08-12

申请号：US09219081

申请日：1998-12-22

申请人： Alain Blanc ,  Pierre Debord ,  Alain Saurel ,  Bernard Brezzo

发明人： Alain Blanc ,  Pierre Debord ,  Alain Saurel ,  Bernard Brezzo

IPC分类号： H04L1256

CPC分类号： H04L49/3081 ,  H04L49/1507 ,  H04L49/201 ,  H04L49/25 ,  H04L49/50 ,  H04L49/506 ,  H04L2012/563 ,  H04L2012/5672 ,  H04Q11/0478

摘要： A flow control process for a switching system having at least one switch core connected through serial communication links to remote and distributed Protocol Adapters or Protocol Engines through Switch Core Access Layer (SCAL) elements. For each input port i, the SCAL element contains a receive Protocol Interface corresponding to the adapter assigned to the input port i and a first serializer for providing attachment to the switch core by means of a first serial communication link. When the cells are received in the switch core, they are deserialized by means of a first deserializer. At each output port, the cells are serialized again by means of a second serializer and then transmitted via a second serial communication link, to the appropriate SCAL. The SCAL contains a second deserializer and a transmit Protocol Interface circuit for permitting attachment of the Protocol Adapter. The flow control process permits two flow control signals, a flow control receive (FCR) from the core to the SCAL, and a flow control transmit (FCX) from the SCAL back to the core. For transmission of the FCR signal in response to the detection of local saturation in the switch core, the process causes transfer of an internal FCR signal to the serializer located within the saturated core. The FCR is introduced in the normal data flow to be conveyed through the second serial link to the remote SCAL corresponding to the saturated input port of the core. An internal control signal can be transmitted to the Protocol Interface that is originating too many cells which results in the overloaded input port of the core. For the transmission of the FCX signal in response to the detection of a saturated Protocol Interface element at one output port, the process generates an internal control signal to the serializer located in the SCAL element. The serializer can introduce a FCX signal in the normal data flow which is conveyed to the core and then decoded by the deserializer in the core. Thus, the core can be informed of the saturation condition that has occurred in the considered output port. Particular adaptations are provided in which the switching system is arranged in a set of individual switching structures mounted in a port expansion mode.

公开(公告)号：US6108334A

公开(公告)日：2000-08-22

申请号：US992871

申请日：1997-12-17

申请人： Alain Blanc ,  Bernard Brezzo ,  Michel Poret ,  Alain Saurel

发明人： Alain Blanc ,  Bernard Brezzo ,  Michel Poret ,  Alain Saurel

IPC分类号： H04L12/70 ,  H04L12/933 ,  H04L12/935 ,  H04Q11/04 ,  H04L12/56

CPC分类号： H04L49/3081 ,  H04L49/1553 ,  H04Q11/0478 ,  H04L2012/5642

摘要： A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit, which includes at least one first FIFO storage for storing the cells being received, receives the data cells from the attached Protocol Adapter and introduces at least one extra byte to every cell. Each transmit part of the destination circuit, which includes at least one second FIFO storage having a greater capacity than the first FIFO storage, receives all the cells that are generated at the corresponding output port and uses the at least one extra byte for cell buffering. Additionally, each distrubuted SCAL element comprises control means for performing Time Division Multiplexing access of the FIFOs.

摘要翻译： 一种交换系统，包括用于将一组M个输入端口的单元路由到一组M个输出端口的交换结构。 该系统包括一组分布式的交换机核心接入层元件，它们通过一组串行通信链路与交换结构的一个输入和输出端口通信。 每个SCAL元件提供至少一个协议适配器的附件，并且包括一组电路。 每个电路的接收部分包括至少一个用于存储接收的单元的第一FIFO存储器，从附加的协议适配器接收数据单元，并向每个单元引入至少一个额外的字节。 目的地电路的每个发送部分包括具有比第一FIFO存储器更大的容量的至少一个第二FIFO存储器，接收在相应输出端口处生成的所有单元，并使用该至少一个额外字节用于单元缓冲。 另外，每个分散的SCAL元件包括用于执行FIFO的时分多路复用访问的控制装置。

公开(公告)号：US06661786B1

公开(公告)日：2003-12-09

申请号：US09315446

申请日：1999-05-20

申请人： Jean-Claude Abbiate ,  Alain Blanc ,  Bernard Brezzo ,  Sylvie Gohl ,  Michel Poret

发明人： Jean-Claude Abbiate ,  Alain Blanc ,  Bernard Brezzo ,  Sylvie Gohl ,  Michel Poret

IPC分类号： H04L1250

CPC分类号： H04L49/1523 ,  H04L49/552

摘要： A service message system for a switching architecture including at least one Switch Fabric (10, 20) comprising a switch core (15, 25) located in a centralized building and a set of Switch Core Access Layer (SCAL) elements distributed in different physical areas for the attachment to the different Port adapters (30, 31). Each SCAL elements particularly includes a SCAL receive element (11-i) and a SCAL Xmit element (12-i) for the respective access to one input port and one output port via serial links. The service message is based on the use of a Cell qualifier field at the beginning of each cell, which comprises a first and a second field. The first field is the Filtering Control field which permits an easy decoding of a service message cell, when applicable. The second field is used for determining which particular type of service message is conveyed via the cell. Following the Cell qualifier is the Switch Routing Header (SRH) which permits the characterization of the destination of the cell and is used for controlling the routing process. Preferably, the service message is used in a fault tolerance configuration where two different Switch Fabrics act as a standby to each other and shares a part of the traffic. Each one is configured as a default routing path for some ports adapters and a backup path for the others. In that particular configuration, the service message system of the invention uses the first field of the Cell qualifier to transport a Direct filtering command causing the Switch fabric to route the cell when the SRH is representative of its default output port destination. Conversely, the first field may transport a Reverse filtering command in the first field that causes the Switch fabric to reverse the default routing process. The first field is also used for characterizing a service message cell which the second field indicates the accurate type. Particularly, two types are used for the production of the filling cells when no data cell is to be transmitted at a particular location of the switching architecture.

公开(公告)号：US06343081B1

公开(公告)日：2002-01-29

申请号：US09121992

申请日：1998-07-24

申请人： Alain Blanc ,  Bernard Brezzo ,  Pierre Debord ,  Patrick Jeanniot ,  Alain Saurel

发明人： Alain Blanc ,  Bernard Brezzo ,  Pierre Debord ,  Patrick Jeanniot ,  Alain Saurel

IPC分类号： H04L1256

CPC分类号： H04L49/3081 ,  H04L12/5601 ,  H04L49/1507 ,  H04L49/1553 ,  H04L49/201 ,  H04L49/25 ,  H04L49/506 ,  H04L2012/5679

摘要： A method and apparatus for managing contention in a self-routing switching architecture based on a set of n×n individual switching structures that are connected in a port expansion mode by means of fan-out and fan-in circuits providing access of the Switch Core Access Layer (SCAL) to the different input and output ports of the switching core. The fan-in circuits use an arbitration mechanism for providing a token to the switch that is allowed to deliver the next cell and the arbiter operates from a detection of a special comma character in accordance with the 8B/10B coding scheme which is introduced in the data flow between the individual switching structures and the fan-in circuits. This provides a compensation for the difference in transfer delays of the cells even when high switching speed and long length of the physical media are involved.

摘要翻译： 一种用于管理自路由交换架构中的争用的方法和装置，所述方法和装置基于通过扇出方式连接的端口扩展模式的一组nxn个别交换结构，以及提供交换机核心接入层 （SCAL）到交换核心的不同输入和输出端口。 扇入电路使用仲裁机制，用于向交换机提供令牌，该令牌被允许传送下一个小区，并且仲裁器根据在8B中引入的8B / 10B编码方案的特殊逗号字符的检测来操作 各个开关结构和扇入电路之间的数据流。 即使涉及物理介质的高切换速度和长的长度，这也为单元的传送延迟的差异提供了补偿。

公开(公告)号：US06570845B1

公开(公告)日：2003-05-27

申请号：US09317322

申请日：1999-05-24

申请人： Alain Blanc ,  Bernard Brezzo ,  Alain Saurel

发明人： Alain Blanc ,  Bernard Brezzo ,  Alain Saurel

IPC分类号： G06F1100

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/153 ,  H04L49/256 ,  H04L49/309 ,  H04L2012/5627 ,  H04L2012/5681

摘要： A switching system receives a data cell from a set of n input ports for routing to one or more output ports in accordance with the contents of a bitmap value retrieved from the cell upon its receipt. The system has a module comprising a shared buffer for storing the cells which are to be routed and a mask mechanism with a mask register for altering the value of the bitmap before it is used for controlling the routing process. As a result of operation of the mask mechanism, a cell is either transported to an output port or discarded. Two switching systems are combined in first and second switch fabrics, each having a switch core and a set of switch core access layer (SCAL) elements. Each SCAL element respectively comprises a SCAL Receive element and a SCAL Xmit element for permitting access to input and output ports of one of the switching systems.

摘要翻译： 交换系统根据从单元接收到的位图值的内容，从一组n个输入端口接收用于路由到一个或多个输出端口的数据单元。 该系统具有模块，该模块包括用于存储待路由的单元的共享缓冲器和具有用于在用于控制路由过程之前改变位图的值的掩码寄存器的掩码机制。 作为掩模机构的操作的结果，单元被传送到输出端口或被丢弃。 两个交换系统组合在第一和第二交换机结构中，每个具有交换机核心和一组交换机核心接入层（SCAL）元件。 每个SCAL元件分别包括SCAL接收元件和SCAL Xmit元件，用于允许访问一个交换系统的输入和输出端口。

公开(公告)号：US6055235A

公开(公告)日：2000-04-25

申请号：US992232

申请日：1997-12-17

申请人： Alain Blanc ,  Christian Landry ,  Michel Poret ,  Jean-Claude Robbe

发明人： Alain Blanc ,  Christian Landry ,  Michel Poret ,  Jean-Claude Robbe

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04L12/931 ,  H04L12/935 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/203 ,  H04L49/3081 ,  H04L2012/5625 ,  H04L2012/563 ,  H04L2012/5652 ,  H04L2012/5681

摘要： A cell switching module and switching system for routing cells each having a cell header comprising a plurality of input and output ports; at least one common cell storage connected between the input and output ports and comprising a plurality of storage locations having addresses; a storage section for performing storage of cells coming through any one of the input ports into the common cell storage and comprising a plurality of receiver means for performing the physical interface for the plurality of input ports, a plurality of input routers for connection the input ports to the cell storage, a plurality of ASA registers for providing the input routers with addresses to be used for storing the cells into the cell storage; and a retrieve section for retrieving cells from storage and for transporting them to one of the output ports, where the retrieve section comprises a plurality of output routers for retrieving the data stored in any locations of the cell storage, a plurality of drivers for connecting to the output ports, and a plurality of ARA registers for providing addresses of the cells which are to be outputted from the cell storage to the output routers.

摘要翻译： 一种用于路由每个具有包括多个输入和输出端口的小区头的小区的小区切换模块和交换系统; 连接在所述输入和输出端口之间的至少一个公共小区存储器，并且包括具有地址的多个存储位置; 存储部分，用于执行将通过任何一个输入端口的单元存储到公共单元存储器中，并且包括用于执行多个输入端口的物理接口的多个接收器装置;多个输入路由器，用于连接输入端口 多个ASA寄存器，用于向所述输入路由器提供用于将所述单元存储到所述单元存储器中的地址; 以及用于从存储器检索单元并将其传送到输出端口之一的检索部分，其中检索部分包括用于检索存储在单元存储器的任何位置的数据的多个输出路由器，多个用于连接到 输出端口和多个ARA寄存器，用于提供要从单元存储器输出到输出路由器的单元的地址。

公开(公告)号：US5359709A

公开(公告)日：1994-10-25

申请号：US826504

申请日：1992-01-27

申请人： Alain Blanc ,  Sylvie Gohl-Roux ,  Gottfried Ungerboeck

发明人： Alain Blanc ,  Sylvie Gohl-Roux ,  Gottfried Ungerboeck

IPC分类号： H04L5/00 ,  H04L27/00 ,  H04L29/06 ,  H04L29/10 ,  G06F13/42

CPC分类号： H04L29/06 ,  H04L27/00

摘要： Multiple operating configurations in data circuit terminating equipment (DCE) are enabled through multiple queues stored in a random access memory and which are loaded with bits and characters coming either from data terminating equipment (DTE) or the telecommunications line. The DSP processor stores bits provided by a transmit circuit in a first queue, determines characters from the bits stored in the first queue based on a first transmission protocol and stores the characters in a second queue. A third queue is used by a control processor to store characters to be transmitted to a remote DCE. The DSP processor determines bits to be transmitted from the characters stored in a third queue based on a second transmission protocol, and stores those bits in a fourth queue. When the DCE is operating in a synchronous mode, the DSP processor determines PCM words for transmission based on the contents of the second queue and stores them in a fifth queue for transmission. Similarly, when the DCE switches to an asynchronous mode, the DSP processor determines PCM words based on the contents of the fourth queue and stores them in the fifth queue for transmission. A similar queue arrangement is provided for the receive circuitry of the DCE.

摘要翻译： 数据电路终端设备（DCE）中的多种操作配置通过存储在随机存取存储器中的多个队列启用，并且装载有来自数据终端设备（DTE）或电信线路的位和字符。 DSP处理器将由发送电路提供的位在第一队列中存储，基于第一传输协议从存储在第一队列中的比特确定字符，并将该字符存储在第二队列中。 控制处理器使用第三个队列来存储要发送到远程DCE的字符。 DSP处理器基于第二传输协议确定从存储在第三队列中的字符发送的比特，并将这些比特存储在第四队列中。 当DCE工作在同步模式时，DSP处理器根据第二个队列的内容来确定用于传输的PCM字，并将其存储在第五个队列中进行传输。 类似地，当DCE切换到异步模式时，DSP处理器基于第四队列的内容来确定PCM字，并将它们存储在第五队列中以进行传输。 为DCE的接收电路提供了类似的队列布置。

公开(公告)号：US06667955B1

公开(公告)日：2003-12-23

申请号：US09315907

申请日：1999-05-20

申请人： Alain Blanc ,  Sylvie Gohl ,  Alain Pinzaglia ,  Menahem Kaplan

发明人： Alain Blanc ,  Sylvie Gohl ,  Alain Pinzaglia ,  Menahem Kaplan

IPC分类号： H04J116

CPC分类号： H04Q3/52 ,  H04L12/5601 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/455 ,  H04L2012/5609 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13167 ,  H04Q2213/13353

摘要： A Switch Fabric system comprising at least one Switch Fabric subsystem (100, 200) further including a set of Switch cores elements (111, 112, 121, 122) that are mounted in a port expansion permitting attachment of at least a first and second sets of Protocol Adapters (1, 2) under a routing control process. A Primary Switch controller (PSC) has a complete knowledge of the topology of the switch, e.g., the number of subsystems, the nature of the port expansion etc., while each Secondary Switch Controller only has a limited knowledge of that topology. One particular Switch Core (111, 211) which has a full-duplex communication capability in each Subsystem is assigned the key function to interface communication between the PSC and the other SSC in a same Switch Fabric Subsystem.

摘要翻译： 一种交换矩阵系统，包括至少一个交换结构子系统（100,200），其还包括一组交换机核心元件（111,112,121,122），其安装在端口扩展中，允许至少连接第一和第二组 的协议适配器（1,2）。 主交换机控制器（PSC）完全了解交换机的拓扑结构，例如子系统的数量，端口扩展的性质等等，而每个辅助交换机控制器只对该拓扑结构的知识有限。 在每个子系统中具有全双工通信能力的特定交换机核心（111,211）被分配为在相同交换结构子系统中的PSC和其他SSC之间的通信的关键功能。

公开(公告)号：US6125114A

公开(公告)日：2000-09-26

申请号：US992015

申请日：1997-12-17

申请人： Alain Blanc ,  Laurent Nicolas ,  Sylvie Gohl

发明人： Alain Blanc ,  Laurent Nicolas ,  Sylvie Gohl

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/937 ,  H04Q11/04 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/1553 ,  H04L49/203 ,  H04L49/255 ,  H04L49/309 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5672

摘要： A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit includes means for introducing at least one extra byte to every cell. The extra byte is reserved for carrying a routing header for controlling the switching structure in a first step, and then for use by the PINT circuit when the cell will be received by the transmit part in a second step. The transmit part of each PINT circuit comprises a control module that receives all the cells generated at the corresponding output port and controls whether to discard the cell based on the value of the extra byte.

摘要翻译： 一种交换系统，包括用于将一组M个输入端口的单元路由到一组M个输出端口的交换结构。 该系统包括一组分布式的交换机核心接入层元件，它们通过一组串行通信链路与交换结构的一个输入和输出端口通信。 每个SCAL元件提供至少一个协议适配器的附件，并且包括一组电路。 每个电路的接收部分包括用于向每个单元引入至少一个额外字节的装置。 额外的字节被保留用于携带用于在第一步骤中控制交换结构的路由报头，然后由PINT电路用于第二步中由发送部分接收信元。 每个PINT电路的发送部分包括控制模块，其接收在相应输出端口处生成的所有单元，并根据额外字节的值来控制是否丢弃该单元。