公开(公告)号：US06661786B1

公开(公告)日：2003-12-09

申请号：US09315446

申请日：1999-05-20

申请人： Jean-Claude Abbiate ,  Alain Blanc ,  Bernard Brezzo ,  Sylvie Gohl ,  Michel Poret

发明人： Jean-Claude Abbiate ,  Alain Blanc ,  Bernard Brezzo ,  Sylvie Gohl ,  Michel Poret

IPC分类号： H04L1250

CPC分类号： H04L49/1523 ,  H04L49/552

摘要： A service message system for a switching architecture including at least one Switch Fabric (10, 20) comprising a switch core (15, 25) located in a centralized building and a set of Switch Core Access Layer (SCAL) elements distributed in different physical areas for the attachment to the different Port adapters (30, 31). Each SCAL elements particularly includes a SCAL receive element (11-i) and a SCAL Xmit element (12-i) for the respective access to one input port and one output port via serial links. The service message is based on the use of a Cell qualifier field at the beginning of each cell, which comprises a first and a second field. The first field is the Filtering Control field which permits an easy decoding of a service message cell, when applicable. The second field is used for determining which particular type of service message is conveyed via the cell. Following the Cell qualifier is the Switch Routing Header (SRH) which permits the characterization of the destination of the cell and is used for controlling the routing process. Preferably, the service message is used in a fault tolerance configuration where two different Switch Fabrics act as a standby to each other and shares a part of the traffic. Each one is configured as a default routing path for some ports adapters and a backup path for the others. In that particular configuration, the service message system of the invention uses the first field of the Cell qualifier to transport a Direct filtering command causing the Switch fabric to route the cell when the SRH is representative of its default output port destination. Conversely, the first field may transport a Reverse filtering command in the first field that causes the Switch fabric to reverse the default routing process. The first field is also used for characterizing a service message cell which the second field indicates the accurate type. Particularly, two types are used for the production of the filling cells when no data cell is to be transmitted at a particular location of the switching architecture.

公开(公告)号：US06597656B1

公开(公告)日：2003-07-22

申请号：US09317006

申请日：1999-05-24

申请人： Alain Blanc ,  Sylvie Gohl ,  Alain Saurel ,  Bernard Brezzo ,  Jean-Claude Robbe

发明人： Alain Blanc ,  Sylvie Gohl ,  Alain Saurel ,  Bernard Brezzo ,  Jean-Claude Robbe

IPC分类号： H04L122

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/309 ,  H04L49/455 ,  H04L2012/5627 ,  H04L2012/5647

摘要： A switching system having at least two switch fabrics. Each fabric has a switch core and a set of SCAL (Switch Core Access Layer) receive and transmit elements. The switch cores are preferably located in the same physical area but the SCALs may be distributed in different physical areas. Port Adapters distributed at different physical areas are connected to the switch fabrics via a particular SCAL element so that each switch core can receive cells from any port adapter and conversely any port adapter may receive data from either switch core. Control logic assigns a particular switch core to one port adapter for normal operations while reserving the other switch core for use when the first core is out of service. Each switch core has a mask mechanism which uses the value in a mask register to alter a bitmap value which controls the routing process. The mask registers in the two switch cores are loaded with complementary values.

摘要翻译： 一种具有至少两个交换结构的交换系统。 每个结构具有交换机核心和一组SCAL（交换机核心接入层）接收和发送元素。 交换机核心优选地位于相同的物理区域中，但是SCAL可以分布在不同的物理区域中。 分布在不同物理区域的端口适配器通过特定的SCAL元件连接到交换结构，使得每个交换机核心可以从任何端口适配器接收单元，相反，任何端口适配器可以从交换机核心接收数据。 控制逻辑将特定的交换机核心分配给一个端口适配器进行正常操作，同时在第一个核心停止工作时保留另一个交换机内核以供使用。 每个交换机核心都有一个掩码机制，使用掩码寄存器中的值来更改控制路由进程的位图值。 两个交换机核心中的掩码寄存器加载互补值。

公开(公告)号：US06411599B1

公开(公告)日：2002-06-25

申请号：US09204394

申请日：1998-12-02

申请人： Alain Blanc ,  Sylvie Gohl ,  Michel Poret

发明人： Alain Blanc ,  Sylvie Gohl ,  Michel Poret

IPC分类号： H04L122

CPC分类号： H04L49/557 ,  H04L1/22 ,  H04L12/5601 ,  H04L49/103 ,  H04L49/30 ,  H04L49/45 ,  H04L2012/5627

摘要： A fault tolerant switching architecture is provided with two separate switch fabrics each having a switch cure located in a centralized building and a set of SCAL elements distributed in different physical areas. Each SCAL element has both a SCAL receive element and a SCAL transmit element for access to a corresponding input and output port of the swatch core. A set of port adapters is distributed at different physical areas, with each connected switch fabrics via a particular SCAL element so that each switch core receives the sequence of cells coming from any port adapter and conversely any port adapter may receive cells from either one of the switch cores. Each switch fabric can detect an internal breakdown condition occurring in one of its element and send an error control signal to the peer element located in the other switch fabric. Each switch core extracts the Switch Routing Header (SRH) from the cells entering the switch core, and a routing table for obtaining a bit map value that indicates the output ports to which the cell should be routed. An additional controllable masking mechanism is used for altering the value of the bit map in response to the detection of the error control signal from the peer switch core. The routing process is then performed with the altered value of the bitmap.

摘要翻译： 具有两个单独的交换结构的容错交换体系结构，每个开关结构具有位于集中式建筑物中的开关固化和分布在不同物理区域中的一组SCAL元件。 每个SCAL元件都具有SCAL接收元件和SCAL传输元件，用于访问样本核心的相应输入和输出端口。 一组端口适配器分布在不同的物理区域，每个连接的交换结构经由特定的SCAL元件，使得每个交换机核心接收来自任何端口适配器的单元序列，并且相反，任何端口适配器可以接收来自 开关核心。 每个交换结构可以检测在其元件之一中发生的内部故障状况，并向位于另一个交换结构中的对等元件发送错误控制信号。 每个交换机核心从进入交换机核心的小区提取交换路由报头（SRH），以及路由表，用于获取指示该小区应路由的输出端口的位图值。 响应于来自对等交换机核心的错误控制信号的检测，使用附加的可控掩蔽机制来改变位图的值。 然后使用位图的改变值执行路由过程。

公开(公告)号：US6108334A

公开(公告)日：2000-08-22

申请号：US992871

申请日：1997-12-17

申请人： Alain Blanc ,  Bernard Brezzo ,  Michel Poret ,  Alain Saurel

发明人： Alain Blanc ,  Bernard Brezzo ,  Michel Poret ,  Alain Saurel

IPC分类号： H04L12/70 ,  H04L12/933 ,  H04L12/935 ,  H04Q11/04 ,  H04L12/56

CPC分类号： H04L49/3081 ,  H04L49/1553 ,  H04Q11/0478 ,  H04L2012/5642

摘要： A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit, which includes at least one first FIFO storage for storing the cells being received, receives the data cells from the attached Protocol Adapter and introduces at least one extra byte to every cell. Each transmit part of the destination circuit, which includes at least one second FIFO storage having a greater capacity than the first FIFO storage, receives all the cells that are generated at the corresponding output port and uses the at least one extra byte for cell buffering. Additionally, each distrubuted SCAL element comprises control means for performing Time Division Multiplexing access of the FIFOs.

摘要翻译： 一种交换系统，包括用于将一组M个输入端口的单元路由到一组M个输出端口的交换结构。 该系统包括一组分布式的交换机核心接入层元件，它们通过一组串行通信链路与交换结构的一个输入和输出端口通信。 每个SCAL元件提供至少一个协议适配器的附件，并且包括一组电路。 每个电路的接收部分包括至少一个用于存储接收的单元的第一FIFO存储器，从附加的协议适配器接收数据单元，并向每个单元引入至少一个额外的字节。 目的地电路的每个发送部分包括具有比第一FIFO存储器更大的容量的至少一个第二FIFO存储器，接收在相应输出端口处生成的所有单元，并使用该至少一个额外字节用于单元缓冲。 另外，每个分散的SCAL元件包括用于执行FIFO的时分多路复用访问的控制装置。

公开(公告)号：US06522269B2

公开(公告)日：2003-02-18

申请号：US09938082

申请日：2001-08-23

申请人： Jean-Claude Abbiate ,  Alain Blanc ,  Francois Le Maut

发明人： Jean-Claude Abbiate ,  Alain Blanc ,  Francois Le Maut

IPC分类号： H03M520

CPC分类号： H03M5/16

摘要： The system and method encodes a binary sequence of data bits into a sequence of ternary symbols and transmits the sequence of ternary symbols over a communication link. The encoding is performed so that no two consecutive symbols of the sequence are alike. The system and method assume that, for encoding, the previously encoded non-null symbol and the previously encoded symbol must be stored in a memory system. The sequence of symbols is transmitted in lieu of the binary sequence of data bits and decoded by a receiving device in order to restore the binary sequence of data bits from the received sequence of symbols. The decoding procedure assumes that three symbols must be received before a bit can be recovered. Hence, the system and method allow a self-delineation or self-sampling of a very-high speed data communication interface that is insensitive to large timing variations and skews.

公开(公告)号：US5461641A

公开(公告)日：1995-10-24

申请号：US981157

申请日：1992-11-23

申请人： Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Gerard Richter

发明人： Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Gerard Richter

IPC分类号： H03M3/04 ,  H03H17/06 ,  H04B14/04

CPC分类号： H03H17/0664

摘要： A Decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of Pulse Coded Modulation (PCM) samples in accordance with the formula ##EQU1## where Cn is the sequence of the coefficients of the decimation filter which corresponds to a determined decimation factor, and the PCM samples being processed by a Digital Signal Processor (DSP). The decimation filter includes a device for storing a digital value representative of the DC component introduced during the sigma-delta coding process, with the digital value being computing by the DSP processor during an initialization phase. The decimation filter further includes a device operating after the latter initialization phase for subtracting the stored digital value from each of the PCM samples so that the resulting sequence of PCM samples appears free of any DC component introduced during the sigma-delta coding. This accurate DC component suppression is achieved without necessitating the use of additional digital signal processor resources from the processor. Preferably, the decimation filter comprises a device for detecting a saturation occurring in the computing of the PCM sample, and responsive to the saturation detection, for transmitting a predetermined PCM sample to the DSP processor.

摘要翻译： 一种抽取滤波器，用于根据与之对应的抽取滤波器的公式来将与Σ-Δ时钟（fs）同步的Σ-Δ脉冲序列转换成脉冲编码调制（PCM）采样序列 到确定的抽取因子，并且PCM采样由数字信号处理器（DSP）处理。 抽取滤波器包括用于存储代表在Σ-Δ编码处理期间引入的DC分量的数字值的装置，数字值由DSP处理器在初始化阶段期间计算。 抽取滤波器还包括在后一初始化阶段之后操作的装置，用于从每个PCM样本中减去所存储的数字值，使得所得到的PCM样本序列在Σ-Δ编码期间不会出现任何DC分量。 实现这种精确的DC分量抑制，而不需要使用来自处理器的附加数字信号处理器资源。 优选地，抽取滤波器包括用于检测在PCM采样的计算中出现的饱和度并且响应饱和检测用于将预定的PCM采样发送到DSP处理器的装置。

公开(公告)号：US5329553A

公开(公告)日：1994-07-12

申请号：US878128

申请日：1992-05-04

申请人： Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Gerard Richter

发明人： Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Gerard Richter

IPC分类号： H04B14/06 ,  H03H17/06 ,  H04L7/06

CPC分类号： H03H17/0614 ,  H03H17/0664

摘要： A decimation filter for converting a received train of sigma-delta pulses in synchronism with a sigma-delta clock (fs) into a train of Pulse Code Modulation (PCM) samples having a PCM clock in accordance with the formula ##EQU1## includes a computer for computing one PCM sample from a sequence of sigma-delta samples in synchronism with the PCM clock and also a comparison circuit for determining whether phase correction of the PCM clock is necessary to lock the generation of the PCM samples on the sigma-delta clock extracted from the received sigma-delta signal, the decimation filter including shifters which shift the computation process at least one sigma-delta clock pulse in order to provide phase control in the generation of the PCM samples.

摘要翻译： 用于将接收到的Σ-Δ脉冲序列与Σ-Δ时钟（fs）同步转换成具有根据公式“IMAGE”的PCM时钟的脉冲编码调制（PCM）采样序列的抽取滤波器包括计算机 用于从与PCM时钟同步的一系列Σ-Δ样本计算一个PCM采样，并且还包括一个比较电路，用于确定PCM时钟的相位校正是否需要在提取的Σ-Δ时钟上锁定PCM采样的产生 从所接收的Σ-Δ信号中，抽取滤波器包括使运算处理至少一个Σ-Δ时钟脉冲移位的移位器，以便在生成PCM采样时提供相位控制。

公开(公告)号：US5315622A

公开(公告)日：1994-05-24

申请号：US754104

申请日：1991-09-03

申请人： Jean-Claude Abbiate ,  Alain Blanc ,  Gottfried Ungerboeck

发明人： Jean-Claude Abbiate ,  Alain Blanc ,  Gottfried Ungerboeck

IPC分类号： H04L7/02 ,  H04L7/033 ,  H04L27/00 ,  H04L27/24 ,  H04L29/10 ,  H04L7/00

CPC分类号： H04L27/24 ,  H04L27/00 ,  H04L7/0331

摘要： Data Circuit Terminating Equipment (DCE) allows the connection of a Data Terminal Equipment (DTE) to a telecommunication line. The DCE includes timing elements for providing the DTE with any desired transmitter signal element timing and any desired receiver signal element timing. The timing elements include processing elements for computing a sequence of digital values A(n) and for deriving therefrom a corresponding sequence of interrupt signals T(n). The receiver signal element timing, the transmitter signal element timing, the transmit sampling clock pulsing the D/A converter and the receive sampling clock pulsing the A/D converter are all controlled by different sequences of digital values computed by the processing elements. By generating appropriate sequences of digital values, the processing elements can provide any desired relationship between the different clocks to satisfy a transmit signal element timing slaved to the receiver signal element timing in synchronous mode, or on an external clock in tailing mode. The timing elements can also provide a transmit sampling clock slaved to the receive sampling clock in order to perform powerful digital echo cancellation techniques. Moreover, the processing elements can control the persistence of a received bit, which if a STOP bit, can allow the compensation of the DTE and the line data throughput difference.

摘要翻译： 数据电路终端设备（DCE）允许将数据终端设备（DTE）连接到电信线路。 DCE包括用于向DTE提供任何期望的发射机信号元素定时和任何期望的接收机信号元素定时的定时元件。 定时元件包括用于计算数字值A（n）的序列的处理元件，并由此导出相应的中断信号序列T（n）。 接收器信号元件定时，发送器信号元件定时，脉冲D / A转换器的发送采样时钟和脉冲A / D转换器的接收采样时钟都由处理元件计算的不同数字值序列控制。 通过产生数字值的适当序列，处理元件可以在不同时钟之间提供任何期望的关系，以满足在同步模式下或者在拖尾模式下的外部时钟在从属于接收机信号元件定时的发射信号元素定时。 定时元件还可以提供从属于接收采样时钟的发射采样时钟，以执行强大的数字回波消除技术。 此外，处理元件可以控制接收位的持续性，如果STOP位可以允许补偿DTE和线数据吞吐量差。

公开(公告)号：US5220327A

公开(公告)日：1993-06-15

申请号：US878106

申请日：1992-05-04

申请人： Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Gerard Orengo ,  Gerard Richter

发明人： Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Gerard Orengo ,  Gerard Richter

IPC分类号： H04B14/06 ,  H03H17/06

CPC分类号： H03H17/0614 ,  H03H17/0664

摘要： A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of PCM samples which includes counters (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storages (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and incrementers (327, 337, 347) driven by the sigma-delta clock fs for incrementing the storages with the incrementation parameter DELTA(n). Finally, the decimation filter includes computers (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storages and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3.times.N input sigma-delta samples according to the formula: ##EQU1##

公开(公告)号：US4941151A

公开(公告)日：1990-07-10

申请号：US252303

申请日：1988-10-03

申请人： Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Eric Lallemand

发明人： Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Eric Lallemand

IPC分类号： H04L7/033

CPC分类号： H04L7/0331

摘要： A predictive clock extracting circuit having a first circuit for determining the duration between two consecutive transitions of a multilevel digital signal and a second circuit for generating an SPL pulse at half the duration after a third transition following on two consecutive previous transitions. A phase locked oscillator which is driven by said SPL pulse generates the extracted clock signal which is in phase with the SPL pulse and coincides with the center of the eye intervals of said multilevel digital signal. The system includes a first counter N which starts running in response to the detection of the first transition of the multilevel digital signal. The running stops when the second transition occurs. The result N(i) stored into the first counter N at second transition is therefore representative of the duration between the two consecutive first and second transitions. The preferred embodiment of the invention also involves an up/down counter K which generates a second counter K(i) that is expected to be representative of half the value of the first counter N(i). Counter K is adaptively updated by incrementing its current value K(i) by a fixed factor or, on the contrary, by decrementing its current value K(i) by a fixed damping factor.