公开(公告)号：US06399512B1

公开(公告)日：2002-06-04

申请号：US09593968

申请日：2000-06-15

申请人： Alain Blosse ,  Sanjay Thedki ,  Jianmin Qiao ,  Yitzhak Gilboa

发明人： Alain Blosse ,  Sanjay Thedki ,  Jianmin Qiao ,  Yitzhak Gilboa

IPC分类号： H01L2100

CPC分类号： H01L21/76807 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention concerns a method for simultaneously forming a metallization and contact structure in an integrated circuit. The method involves the steps of etching a trench dielectric layer of a composite structure having a semiconductor substrate with an active region, a gate structure thereon, at least one dielectric spacer adjacent to the gate structure, a contact dielectric layer over the semiconductor substrate, the gate structure and the dielectric spacer, an etch stop layer over the contact dielectric layer, and a trench dielectric layer over the etch stop layer, to form a trench in the trench dielectric under etch conditions which do not substantially etch the etch stop layer; thereafter, forming an opening in the etch stop layer and the contact dielectric layer by etching under conditions which do not damage the gate structure to expose the active region; and depositing a conductive material into the opening and the trench.

摘要翻译： 本发明涉及在集成电路中同时形成金属化和接触结构的方法。 该方法包括以下步骤：蚀刻具有半导体衬底的复合结构的沟槽电介质层，所述半导体衬底具有有源区，其上的栅极结构，与栅结构相邻的至少一个电介质衬垫，半导体衬底上的接触电介质层， 栅极结构和电介质间隔物，接触介电层上的蚀刻停止层以及蚀刻停止层上方的沟槽电介质层，以在基本不蚀刻蚀刻停止层的蚀刻条件下在沟槽电介质中形成沟槽; 然后在不损坏栅极结构以暴露有源区的条件下通过蚀刻在蚀刻停止层和接触电介质层中形成开口; 以及将导电材料沉积到开口和沟槽中。

公开(公告)号：US06635566B1

公开(公告)日：2003-10-21

申请号：US09593967

申请日：2000-06-15

申请人： Alain Blosse ,  Sanjay Thedki ,  Jianmin Qiao ,  Yitzhak Gilboa

发明人： Alain Blosse ,  Sanjay Thedki ,  Jianmin Qiao ,  Yitzhak Gilboa

IPC分类号： H01L214763

CPC分类号： H01L21/76801 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76897 ,  H01L2221/1036

摘要： The invention concerns a method for forming metallization and contact structures in an integrated circuit. The method involoves the steps of etching a trench in the trench dielectric layer a trench dielectric layer of a composite structure containing a semiconductor substrate comprising an active region, a gate structure thereover, and dielectric spacers adjacent to the gate structure, a contact dielectric layer; and the trench dielectric layer; etching the contact dielectric layer under conditions which do not damage the gate structure to form a first contact opening that exposes a region of the semiconductor substrate; and depositing a conductive material into the contact opening and the trench.

摘要翻译： 本发明涉及在集成电路中形成金属化和接触结构的方法。 该方法有助于蚀刻沟槽电介质层中的沟槽的步骤，该沟槽电介质层包括包含有源区，其上的栅极结构和与该栅极结构相邻的电介质间隔区的半导体衬底的复合结构;接触电介质层; 和沟槽电介质层; 在不损坏栅极结构以形成暴露半导体衬底的区域的第一接触开口的条件下蚀刻接触电介质层; 以及将导电材料沉积到所述接触开口和所述沟槽中。

公开(公告)号：US07197737B1

公开(公告)日：2007-03-27

申请号：US11016077

申请日：2004-12-17

申请人： Walter Iandolo ,  Yitzhak Gilboa ,  Artur Balasinski

发明人： Walter Iandolo ,  Yitzhak Gilboa ,  Artur Balasinski

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： In one embodiment, a dummy pattern having a plurality of dummy features (e.g., waffles) are employed to help achieve a relatively planar surface by chemical-mechanical planarization (CMP). The dummy features are placed based on a dielectric pattern density of a region of an integrated circuit. The dummy features may be added to the design of the integrated circuit using a one pass or two pass approach. The dummy features in a second pass may be fragmented using an AndNot algorithm, for example.

摘要翻译： 在一个实施例中，使用具有多个虚拟特征（例如，华夫饼）的虚拟图案来帮助通过化学机械平面化（CMP）实现相对平坦的表面。 虚设特征基于集成电路的区域的介电图案密度放置。 虚拟特征可以使用一遍或二次方法添加到集成电路的设计中。 例如，第二遍中的虚拟特征可以使用AndNot算法来分段。

公开(公告)号：US06969684B1

公开(公告)日：2005-11-29

申请号：US09846119

申请日：2001-04-30

申请人： Yitzhak Gilboa ,  William W. C. Koutny, Jr. ,  Steven Hedayati ,  Krishnaswamy Ramkumar

发明人： Yitzhak Gilboa ,  William W. C. Koutny, Jr. ,  Steven Hedayati ,  Krishnaswamy Ramkumar

IPC分类号： H01L21/302 ,  H01L21/3105 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/31053 ,  H01L21/31055

摘要： A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not include a polish stop material. Preferably, the upper surface of the topography formed by polishing is spaced sufficiently above the underlying layer to avoid polishing the underlying layer. The entirety of the upper surface may be simultaneously etched to expose the underlying layer. In an embodiment, the underlying layer may comprise a lateral variation in polish characteristics. The method may include using fixed abrasive polishing of a dielectric layer for reducing a required thickness of an additional layer underlying the dielectric layer. Such a method may be useful when exposing an underlying layer is desirable by techniques other than polishing.

摘要翻译： 提供了一种从抛光过程中消除抛光停止层的方法。 特别地，提供了一种方法，其可以包括抛光半导体形貌的上层以形成在下层之上的高度上的上表面，其中上表面不包括抛光停止材料。 优选地，通过抛光形成的形貌的上表面被充分地间隔在下面的层上，以避免抛光下面的层。 可以同时蚀刻整个上表面以暴露下层。 在一个实施例中，下层可以包括抛光特性的横向变化。 该方法可以包括使用介电层的固定研磨抛光来减少介电层下面的附加层的所需厚度。 当通过除了抛光之外的技术来期望暴露下层时，这种方法可能是有用的。

公开(公告)号：US06833622B1

公开(公告)日：2004-12-21

申请号：US10375534

申请日：2003-02-27

申请人： Andrey V. Zagrebelny ,  Daniel J. Arnzen ,  Yitzhak Gilboa

发明人： Andrey V. Zagrebelny ,  Daniel J. Arnzen ,  Yitzhak Gilboa

IPC分类号： H01L2348

CPC分类号： H01L21/76819 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/76237 ,  Y10S438/926 ,  Y10S438/975

摘要： A dummy structure pattern for fabricating a substantially planar surface within an inactive region of a semiconductor topography is provided. In particular, a semiconductor topography is provided which includes an inactive region comprising a sacrificial annular dummy structure configured to surround an area larger than a square of a minimum critical dimension of a device arranged within an active region of the semiconductor topography. In a preferred embodiment, the area is exclusively designated for a formation of an isolation structure within the semiconductor substrate of the semiconductor topography. As such, a semiconductor topography is provided which includes a separate isolation structure arranged within a spacing of a contiguous isolation structure, which is arranged in a grid pattern within a portion of a semiconductor substrate. Moreover, a semiconductor device is provided which includes an inactive region with a plurality of similarly sized and uniformly arranged annular diffusion regions.

摘要翻译： 提供了一种用于在半导体形貌的非活性区域内制造基本平坦表面的虚拟结构图案。 特别地，提供了半导体形貌，其包括非活性区域，其包括牺牲环形虚设结构，该牺牲环形虚设结构构造成围绕布置在半导体形貌的有源区域内的器件的最小临界尺寸的平方以上。 在优选实施例中，该区域专门用于在半导体拓扑的半导体衬底内形成隔离结构。 因此，提供半导体形貌，其包括布置在邻接隔离结构的间隔内的单独的隔离结构，其以半导体衬底的一部分内的栅格图案布置。 此外，提供一种半导体器件，其包括具有多个相似尺寸且均匀排列的环形扩散区域的非活性区域。