公开(公告)号：US20100032766A1

公开(公告)日：2010-02-11

申请号：US12308158

申请日：2006-06-02

申请人： Alan Sangone Chen ,  Mark Victor Dyson ,  Edward Belden Harris ,  Daniel Charles Kerr ,  William John Nagy

发明人： Alan Sangone Chen ,  Mark Victor Dyson ,  Edward Belden Harris ,  Daniel Charles Kerr ,  William John Nagy

IPC分类号： H01L27/102 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/73

CPC分类号： H01L29/0821 ,  H01L29/404

摘要： A process for forming a bipolar junction transistor (BJT) in a semiconductor substrate and a BJT formed according to the process. A buried isolation region is formed underlying BJT structures to isolate the BJT structures from the p-type semi-conductor substrate. To reduce capacitance between a BJT subcollector and the buried isolation region, prior to implanting the subcollector spaced-apart structures are formed on a surface of the substrate. The subcollector is formed by implanting ions through the spaced-apart structures and through a region intermediate the spaced-apart structures. The formed BJT subcollector therefore comprises a body portion and end portions extending therefrom, with the end portions disposed at a shallower depth than the body portion, since the ions implanting the end portions must pass through the spaced-apart structures. The shallower depth of the end portions reduces the capacitance.

摘要翻译： 在半导体衬底中形成双极结型晶体管（BJT）的工艺和根据该工艺形成的BJT。 在BJT结构之下形成掩埋隔离区，以将BJT结构与p型半导体衬底隔离。 为了减小BJT子集电极和掩埋隔离区之间的电容，在植入之前，在基板的表面上形成间接分离结构的子集电极。 子集电极通过将离子注入间隔开的结构并通过间隔开的结构之间的区域而形成。 因此，形成的BJT子集电极包括主体部分和从其延伸的端部，其端部设置在比主体部分更浅的深度，因为注入端部的离子必须通过间隔开的结构。 端部较浅的深度减小了电容。

公开(公告)号：US07253012B2

公开(公告)日：2007-08-07

申请号：US10941665

申请日：2004-09-14

申请人： Daniel Charles Kerr ,  Roscoe T. Luce ,  Michele Marie Jamison ,  Alan Sangone Chen ,  William A. Russell

发明人： Daniel Charles Kerr ,  Roscoe T. Luce ,  Michele Marie Jamison ,  Alan Sangone Chen ,  William A. Russell

IPC分类号： H01L21/00

CPC分类号： H01L21/0271 ,  H01L23/585 ,  H01L2924/0002 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/95 ,  H01L2924/00

摘要： A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain aspects, two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at least one particular layer for a particular processing step. By the guard ring overwhelming the effect of local features' elevation differences, photoresist thereafter applied consequently has a more uniform height across the interior area, resulting in more uniform devices. A plurality of guard rings may be used that enclose respective arrays of matched devices arranged over the surface of a semiconductor wafer. Based on the equalizing effect by each of the guard rings, the respective devices arranged in the interior areas are more evenly matched to equivalent devices in far-spaced guard rings. Thus, local and global matching are achieved.

摘要翻译： 半导体制造方法包括形成限定内部区域的调平保护环，其中制造了一个或多个装置。 在某些方面，在内部区域中制造两个或多个匹配的装置，例如以共同的质心布局。 保护环形成在用于特定加工步骤的至少一个特定层上。 由于保护环压倒了局部特征的高程差异的影响，因此其后应用的光致抗蚀剂在内部区域具有更均匀的高度，导致更均匀的装置。 可以使用多个保护环，其包围布置在半导体晶片的表面上的匹配器件的相应阵列。 基于每个保护环的均衡效应，布置在内部区域中的各个装置与远距离保护环中的等效装置更均匀地匹配。 因此，实现了局部和全局匹配。

公开(公告)号：US07176781B2

公开(公告)日：2007-02-13

申请号：US10953478

申请日：2004-09-29

申请人： Daniel Charles Kerr ,  Roger W. Key ,  Bradley J. Albers ,  William A. Russell ,  Alan Sangone Chen

发明人： Daniel Charles Kerr ,  Roger W. Key ,  Bradley J. Albers ,  William A. Russell ,  Alan Sangone Chen

IPC分类号： H01C1/012

CPC分类号： H01L23/5228 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resistor formed on a material layer of a semiconductor integrated circuit and a method for forming the resistor. The resistor comprises a region of resistive material with a plurality of conductive contacts or plugs in electrical contact with and extending away from the resistive material. A first and a second interconnect line are formed overlying the plugs and in conductive contact with one or more of the plurality of plugs, such that a portion of the resistive material between the first and the second interconnect lines provides a desired resistance. According to a method of the present invention, the plurality of conductive contacts are formed using a first photolithographic mask and the first and the second interconnect lines are formed using a second photolithographic mask. The desired resistance is changed by modifying the first or the second mask such that one or more dimensions of a region of the resistive material between the first and the second interconnect lines is altered.

摘要翻译： 形成在半导体集成电路的材料层上的电阻器和形成该电阻器的方法。 电阻器包括电阻材料的区域，其具有与电阻材料电接触并远离电阻材料的多个导电触点或插塞。 第一和第二互连线形成在插头上方并与多个插头中的一个或多个导电接触，使得第一和第二互连线之间的电阻材料的一部分提供期望的电阻。 根据本发明的方法，使用第一光刻掩模形成多个导电触点，并且使用第二光刻掩模形成第一和第二布线。 通过修改第一或第二掩模来改变期望的电阻，使得在第一和第二互连线之间的电阻材料的区域的一个或多个维度被改变。

公开(公告)号：US07642617B2

公开(公告)日：2010-01-05

申请号：US11237095

申请日：2005-09-28

申请人： Alan Sangone Chen ,  Daniel J. Dolan, Jr. ,  David W. Kelly ,  Daniel Charles Kerr ,  Stephen C. Kuehne

发明人： Alan Sangone Chen ,  Daniel J. Dolan, Jr. ,  David W. Kelly ,  Daniel Charles Kerr ,  Stephen C. Kuehne

IPC分类号： H01L21/331

CPC分类号： H01L29/808 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/098 ,  H01L29/1066 ,  H01L29/7833

摘要： An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device includes a channel region in the semiconductor layer spaced from, and having a peak concentration positioned a predetermined distance below, the upper surface. An associated method of manufacturing includes introducing p-type dopant into the semiconductor surface to form a p-well in which the NMOS device is formed and a source and a drain of the JFET device. N-type dopant is introduced into the semiconductor surface to form an n-type region of the NMOS device below the p-well and a gate region of the JFET device. P-type dopant is introduced into the semiconductor layer to simultaneously form a higher concentration p-type region in the p-well of the NMOS device and a channel region extending between the source and drain of the JFET.

摘要翻译： 具有n沟道MOSFET器件和JFET器件的集成电路。 集成电路包括具有上表面的半导体层，形成在从半导体上表面延伸的第一导电类型的掺杂阱中的MOS晶体管器件和JFET器件。 JFET器件包括半导体层中的与上表面间隔开并具有位于预定距离的峰值浓度的沟道区域。 相关联的制造方法包括将p型掺杂剂引入半导体表面以形成其中形成NMOS器件的p阱以及JFET器件的源极和漏极。 N型掺杂剂被引入到半导体表面中以在p阱的下面形成NMOS器件的n型区域和JFET器件的栅极区域。 P型掺杂剂被引入到半导体层中，以在NMOS器件的p阱和在JFET的源极和漏极之间延伸的沟道区域中同时形成更高浓度的p型区域。

公开(公告)号：US07345364B2

公开(公告)日：2008-03-18

申请号：US10955238

申请日：2004-09-30

申请人： Daniel Charles Kerr ,  Alan Sangone Chen ,  Edward Paul Martin, Jr. ,  Amal Ma Hamad ,  William A. Russell

发明人： Daniel Charles Kerr ,  Alan Sangone Chen ,  Edward Paul Martin, Jr. ,  Amal Ma Hamad ,  William A. Russell

IPC分类号： H01L23/10 ,  H01L23/34

CPC分类号： H01L23/3677 ,  H01L2224/48091 ,  H01L2924/01327 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： A thermally conductive structure for a semiconductor integrated circuit and a method for making the structure. The structure comprises one or more vertical and/or horizontal thermally conductive elements disposed proximate a device for improving thermal conductivity from the device to a substrate of the integrated circuit. In one embodiment a heat sink is affixed to the integrated circuit for heat flow from the integrated circuit. The method comprises forming openings in material layers overlying the semiconductor substrate, wherein the openings are disposed proximate the device and extend to the substrate. A thermally conductive material is formed in the openings to provide a thermal path from the device to the substrate.

摘要翻译： 一种用于半导体集成电路的导热结构及其制造方法。 该结构包括一个或多个垂直和/或水平导热元件，其设置在靠近器件的位置，以改善从器件到集成电路的衬底的导热性。 在一个实施例中，散热器固定到集成电路以用于来自集成电路的热流。 该方法包括在覆盖半导体衬底的材料层中形成开口，其中开口设置在器件附近并延伸到衬底。 在开口中形成导热材料以提供从器件到衬底的热路径。

公开(公告)号：US07498204B2

公开(公告)日：2009-03-03

申请号：US11968693

申请日：2008-01-03

申请人： Daniel Charles Kerr ,  Alan Sangone Chen ,  Edward Paul Martin, Jr. ,  Amal Ma Hamad ,  William A. Russell

发明人： Daniel Charles Kerr ,  Alan Sangone Chen ,  Edward Paul Martin, Jr. ,  Amal Ma Hamad ,  William A. Russell

IPC分类号： H01L21/00

CPC分类号： H01L23/3677 ,  H01L2224/48091 ,  H01L2924/01327 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： A thermally conductive structure for a semiconductor integrated circuit and a method for making the structure. The structure comprises one or more vertical and/or horizontal thermally conductive elements disposed proximate a device for improving thermal conductivity from the device to a substrate of the integrated circuit. In one embodiment a heat sink is affixed to the integrated circuit for heat flow from the integrated circuit. The method comprises forming openings in material layers overlying the semiconductor substrate, wherein the openings are disposed proximate the device and extend to the substrate. A thermally conductive material is formed in the openings to provide a thermal path from the device to the substrate.

摘要翻译： 一种用于半导体集成电路的导热结构及其制造方法。 该结构包括一个或多个垂直和/或水平导热元件，其设置在靠近器件的位置，以改善从器件到集成电路的衬底的导热性。 在一个实施例中，散热器固定到集成电路以用于来自集成电路的热流。 该方法包括在覆盖半导体衬底的材料层中形成开口，其中开口设置在器件附近并延伸到衬底。 在开口中形成导热材料以提供从器件到衬底的热路径。

公开(公告)号：US07407824B2

公开(公告)日：2008-08-05

申请号：US11748569

申请日：2007-05-15

申请人： Daniel Charles Kerr ,  Roscoe T. Luce ,  Michele Marie Jamison ,  Alan Sangone Chen ,  William A. Russell

发明人： Daniel Charles Kerr ,  Roscoe T. Luce ,  Michele Marie Jamison ,  Alan Sangone Chen ,  William A. Russell

IPC分类号： H01L21/00

CPC分类号： H01L21/0271 ,  H01L23/585 ,  H01L2924/0002 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/95 ,  H01L2924/00

摘要： A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain embodiments two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at least one particular layer for a particular processing step. By the guard ring overwhelming the effect of local features' elevation differences, photoresist thereafter applied consequently has a more uniform height across the interior area, resulting in more uniform devices.In some embodiments, a plurality of guard rings enclosing respective arrays of matched devices are arranged over the surface of a semiconductor wafer, spaced apart so as to be not local to one another. Based on the equalizing effect by each of the guard rings, the respective devices arranged in the interior areas are more evenly matched to equivalent devices in far-spaced guard rings. Thus, both local and global matching are achieved.

摘要翻译： 半导体制造方法包括形成限定内部区域的调平保护环，其中制造了一个或多个装置。 在某些实施例中，在内部区域中制造两个或多个匹配的装置，例如以共同的质心布局。 保护环形成在用于特定加工步骤的至少一个特定层上。 由于保护环压倒了局部特征的高程差异的影响，因此其后应用的光致抗蚀剂在内部区域具有更均匀的高度，导致更均匀的装置。 在一些实施例中，包围匹配装置的相应阵列的多个保护环布置在半导体晶片的表面上，间隔开，以便彼此不是局部的。 基于每个保护环的均衡效应，布置在内部区域中的各个装置与远距离保护环中的等效装置更均匀地匹配。 因此，实现了本地和全局匹配。

公开(公告)号：US09356144B1

公开(公告)日：2016-05-31

申请号：US12854563

申请日：2010-08-11

申请人： Philip Mason ,  Daniel Charles Kerr ,  Michael Carroll

发明人： Philip Mason ,  Daniel Charles Kerr ,  Michael Carroll

IPC分类号： H01L23/62 ,  H01L29/78

CPC分类号： H01L29/7841 ,  H01L27/0255

摘要： The present disclosure relates to gate oxide protection circuits, which are used to protect the gate oxides of field effect transistor (FET) elements from over voltage conditions, particularly during situations in which the gate oxides are particularly vulnerable, such as during certain manufacturing stages. Each gate oxide protection circuit may be coupled to a corresponding FET element through corresponding first and second resistive elements, which are coupled to a corresponding gate connection node and a corresponding first connection node, respectively, of the FET element. The gate connection node and the first connection node are electrically adjacent to opposite sides of the gate oxide of the FET element. Each gate oxide protection circuit may protect its corresponding FET element by limiting a voltage between the gate connection node and the first connection node.

摘要翻译： 本公开涉及栅极氧化物保护电路，其用于保护场效应晶体管（FET）元件的栅极氧化物免受过电压条件，特别是在栅极氧化物特别容易受到影响的情况下，例如在某些制造阶段。 每个栅极氧化物保护电路可以通过对应的第一和第二电阻元件耦合到对应的FET元件，该第一和第二电阻元件分别耦合到FET元件的对应的栅极连接节点和相应的第一连接节点。 栅极连接节点和第一连接节点与FET元件的栅极氧化物的相对侧电气相邻。 每个栅极氧化物保护电路可以通过限制栅极连接节点和第一连接节点之间的电压来保护其对应的FET元件。

公开(公告)号：US08706070B2

公开(公告)日：2014-04-22

申请号：US13272537

申请日：2011-10-13

申请人： Ali Tombak ,  Joshua J. Caron ,  Daniel Charles Kerr

发明人： Ali Tombak ,  Joshua J. Caron ,  Daniel Charles Kerr

IPC分类号： H04B1/10

CPC分类号： H04B1/109 ,  H03H11/16

摘要： An RF system for reducing intermodulation (IM) products is disclosed. The RF system includes a first nonlinear element and a second nonlinear element, wherein the second nonlinear element generates inherent IM products and the first nonlinear element is adapted to generate compensating IM products. Alternatively, the first nonlinear element generates inherent IM products and the second nonlinear element is adapted to generate compensating IM products. The amplitudes of the compensating IM products are substantially equal to amplitudes of the inherent IM products. The RF system further includes a phase shifter that is adapted to provide a phase shift that results in around 180° of phase shift between the inherent IM products and the compensating IM products. The phase shifter is coupled between the first nonlinear element and the second nonlinear element.

摘要翻译： 公开了用于减少互调（IM）产品的RF系统。 RF系统包括第一非线性元件和第二非线性元件，其中第二非线性元件产生固有的IM产品，并且第一非线性元件适于产生补偿IM产品。 或者，第一非线性元件产生固有的IM产品，并且第二非线性元件适于产生补偿IM产品。 补偿IM产品的振幅基本上等于固有IM产品的振幅。 RF系统还包括移相器，其适于提供导致固有IM产品和补偿IM产品之间的相移大约180°的相移。 移相器耦合在第一非线性元件和第二非线性元件之间。

公开(公告)号：US08076750B1

公开(公告)日：2011-12-13

申请号：US12958494

申请日：2010-12-02

申请人： Daniel Charles Kerr ,  Thomas Gregory McKay ,  Michael Carroll ,  Joseph M. Gering

发明人： Daniel Charles Kerr ,  Thomas Gregory McKay ,  Michael Carroll ,  Joseph M. Gering

IPC分类号： H01L29/00

CPC分类号： H01L23/645 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to using a trap-rich layer, such as a polycrystalline Silicon layer, over a semiconductor substrate to substantially immobilize a surface conduction layer at the surface of the semiconductor substrate at radio frequency (RF) frequencies. The trap-rich layer may have a high density of traps that trap carriers from the surface conduction layer. The average release time from the traps may be longer than the period of any present RF signals, thereby effectively immobilizing the surface conduction layer, which may substantially prevent capacitance and inductance changes due to the RF signals. Therefore, harmonic distortion of the RF signals may be significantly reduced or eliminated. The semiconductor substrate may be a Silicon substrate, a Gallium Arsenide substrate, or another substrate.