公开(公告)号：US06548874B1

公开(公告)日：2003-04-15

申请号：US09669391

申请日：2000-09-26

申请人： Alec Morton ,  Taylor Efland ,  Chin-yu Tsai ,  Jozef C. Mitros ,  Dan M. Mosher ,  Sam Shichijo ,  Keith Kunz

发明人： Alec Morton ,  Taylor Efland ,  Chin-yu Tsai ,  Jozef C. Mitros ,  Dan M. Mosher ,  Sam Shichijo ,  Keith Kunz

IPC分类号： H01L2976

CPC分类号： H01L27/092 ,  H01L29/0653 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50), (140) and drain regions (55), (145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70), (80) serve as the drain extension regions of the transistor.

摘要翻译： 用于亚微米CMOS工艺的集成电路漏极延伸晶体管。 在硅衬底（10）中的CMOS n阱区（80）和CMOS p阱区（70）上形成晶体管栅极（40）。 晶体管源极区域（50），（140）和漏极区域（55），（145）形成在各种CMOS阱区域中以形成漏极延伸晶体管，其中CMOS阱区域（70），（80）用作漏极延伸 晶体管的区域。

公开(公告)号：US20070064494A1

公开(公告)日：2007-03-22

申请号：US11230078

申请日：2005-09-19

申请人： Alec Morton ,  Jozef Mitros

发明人： Alec Morton ,  Jozef Mitros

IPC分类号： G11C16/04

CPC分类号： G11C16/0433 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2216/10 ,  H01L27/11519 ,  H01L27/11558 ,  H01L29/7881

摘要： An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM layout that eliminates the use of high voltage transistors from the array core region. If they are utilized, the high voltage transistors are moved to row and column drivers in the periphery region to increase array density with little or no added process complexity to allow economic implementation of larger embedded SLP EEPROM arrays. During program or erase operations of the array, the method provides a programming voltage for the selected memory cells of the array, and a half-write (e.g., mid-level) voltage to the remaining unselected memory cells to avoid disturbing the unselected memory cells of the array.

摘要翻译： 在更高密度的嵌入式EEPROM布局中讨论了单级多NMOS EEPROM存储单元的阵列结构和操作该阵列的方法，其消除了使用阵列核心区域中的高压晶体管。 如果利用它们，则高压晶体管被移动到周边区域中的行和列驱动器以增加阵列密度，很少或没有附加的工艺复杂性，以允许经济地实现更大的嵌入式SLP EEPROM阵列。 在阵列的编程或擦除操作期间，该方法为阵列的所选择的存储单元提供编程电压，并向剩余的未选择的存储单元写入半写（例如，中级）电压，以避免干扰未选择的存储单元 的数组。

公开(公告)号：US20050127516A1

公开(公告)日：2005-06-16

申请号：US10735374

申请日：2003-12-12

申请人： Betty Mercer ,  Alec Morton ,  Byron Williams ,  Laurinda Ng ,  C. Thompson ,  Der-E Jan ,  Sunny Lee ,  Phuong-Lan Thi Tran

发明人： Betty Mercer ,  Alec Morton ,  Byron Williams ,  Laurinda Ng ,  C. Thompson ,  Der-E Jan ,  Sunny Lee ,  Phuong-Lan Thi Tran

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L29/40

CPC分类号： H01L21/76877 ,  H01L21/76838

摘要： The present invention relates to integrated circuits comprising a protective overcoat and thick copper connectors. According to one aspect of the inventions, vias in the protective overcoat are substantially filled with tungsten plugs, or plugs of another metal with a relatively low coefficient of thermal expansion. According to another aspect of the invention, large vias in the protective overcoat are replaced with arrays of smaller vias. The invention reduces the likelihood of device failures during temperature cycling tests. Also, the invention allows for smaller vias in the protective overcoat and removal of interconnect functions to the thick copper layer.

摘要翻译： 本发明涉及包括保护外涂层和厚铜连接器的集成电路。 根据本发明的一个方面，保护性外涂层中的通孔基本上填充有钨塞或具有相对低的热膨胀系数的另一种金属的塞子。 根据本发明的另一方面，保护性外涂层中的大的通孔被更小的通孔的阵列所取代。 本发明降低了温度循环测试期间设备故障的可能性。 此外，本发明允许保护性外涂层中的较小的通孔和去除厚铜层的互连功能。

公开(公告)号：US06591409B2

公开(公告)日：2003-07-08

申请号：US09995555

申请日：2001-11-28

申请人： Ganesh Kamath ,  Preetham Kumar ,  Alec Morton

发明人： Ganesh Kamath ,  Preetham Kumar ,  Alec Morton

IPC分类号： G06F1750

CPC分类号： G06F17/5081

摘要： A method and system of measuring layout efficiency is disclosed wherein after the initial layout (A), and the layout is drawn (B) a layout verification step C includes identifying seed devices or layers and the devices or layers are grown according to design rules and process rules to determine the minimum area required for the design. The layout verification is performed for both device packing density and interconnect packing density and the efficiency is calculated based on the total available area and reported.(D).

公开(公告)号：US20050239277A1

公开(公告)日：2005-10-27

申请号：US10828592

申请日：2004-04-21

申请人： Betty Mercer ,  Erika Shoemaker ,  Byron Williams ,  Laurinda Ng ,  Alec Morton ,  C. Thompson

发明人： Betty Mercer ,  Erika Shoemaker ,  Byron Williams ,  Laurinda Ng ,  Alec Morton ,  C. Thompson

IPC分类号： G03C1/85 ,  H01L21/44 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L2224/039 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an integrated circuit including the interconnect. The interconnect (100), among other elements, includes a surface conductive lead (160) located in an opening formed within a protective overcoat (110), and a barrier layer (140) located between the protective overcoat (110) and the surface conductive lead (160), a portion of the barrier layer (140) forming a skirt (145) that extends outside a footprint of the surface conductive lead (160).

摘要翻译： 本发明提供了一种用于集成电路的互连，一种用于制造该互连的方法，以及一种用于制造包括该互连的集成电路的方法。 除了其它元件之外，互连（100）包括位于形成在保护外涂层（110）内的开口中的表面导电引线（160）和位于保护外涂层（110）和表面导电 导线（160），阻挡层（140）的形成裙部（145）的部分延伸到表面导电引线（160）的覆盖区外部。

公开(公告)号：US20050145922A1

公开(公告)日：2005-07-07

申请号：US10748497

申请日：2003-12-30

申请人： Joseph Farley ,  Jozef Mitros ,  Alec Morton ,  Robert Todd

发明人： Joseph Farley ,  Jozef Mitros ,  Alec Morton ,  Robert Todd

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/7885

摘要： An EEPROM memory cell uses PMOS type floating gate transistor formed in a n-well, where the floating gate is routed over a p− diffused region formed in the n-well to form a control capacitor. The PMOS floating gate transistor uses a p-type diffused region below the p+ active region forming the drain to provide a higher breakdown voltage. Cell programming can be performed through hot-electron injection, with the electric field across the control capacitor to aid injection into the floating gate. FN erasure is achieved by taking the potential of the n-well to the programming voltage while holding the potential of the control capacitor at a low voltage.

摘要翻译： EEPROM存储单元使用形成在n阱中的PMOS型浮栅晶体管，其中浮置栅极在形成在n阱中的p扩散区域上布线以形成控制电容器。 PMOS浮栅晶体管使用形成漏极的p +有源区以下的p型扩散区，以提供更高的击穿电压。 电池编程可以通过热电子注入进行，电容器两端的电场可以帮助注入浮动栅极。 通过将n阱的电位置于编程电压同时将控制电容器的电位保持在低电压下来实现FN擦除。