公开(公告)号：US20050145922A1

公开(公告)日：2005-07-07

申请号：US10748497

申请日：2003-12-30

申请人： Joseph Farley ,  Jozef Mitros ,  Alec Morton ,  Robert Todd

发明人： Joseph Farley ,  Jozef Mitros ,  Alec Morton ,  Robert Todd

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/7885

摘要： An EEPROM memory cell uses PMOS type floating gate transistor formed in a n-well, where the floating gate is routed over a p− diffused region formed in the n-well to form a control capacitor. The PMOS floating gate transistor uses a p-type diffused region below the p+ active region forming the drain to provide a higher breakdown voltage. Cell programming can be performed through hot-electron injection, with the electric field across the control capacitor to aid injection into the floating gate. FN erasure is achieved by taking the potential of the n-well to the programming voltage while holding the potential of the control capacitor at a low voltage.

摘要翻译： EEPROM存储单元使用形成在n阱中的PMOS型浮栅晶体管，其中浮置栅极在形成在n阱中的p扩散区域上布线以形成控制电容器。 PMOS浮栅晶体管使用形成漏极的p +有源区以下的p型扩散区，以提供更高的击穿电压。 电池编程可以通过热电子注入进行，电容器两端的电场可以帮助注入浮动栅极。 通过将n阱的电位置于编程电压同时将控制电容器的电位保持在低电压下来实现FN擦除。

公开(公告)号：US20070064494A1

公开(公告)日：2007-03-22

申请号：US11230078

申请日：2005-09-19

申请人： Alec Morton ,  Jozef Mitros

发明人： Alec Morton ,  Jozef Mitros

IPC分类号： G11C16/04

CPC分类号： G11C16/0433 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2216/10 ,  H01L27/11519 ,  H01L27/11558 ,  H01L29/7881

摘要： An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM layout that eliminates the use of high voltage transistors from the array core region. If they are utilized, the high voltage transistors are moved to row and column drivers in the periphery region to increase array density with little or no added process complexity to allow economic implementation of larger embedded SLP EEPROM arrays. During program or erase operations of the array, the method provides a programming voltage for the selected memory cells of the array, and a half-write (e.g., mid-level) voltage to the remaining unselected memory cells to avoid disturbing the unselected memory cells of the array.

摘要翻译： 在更高密度的嵌入式EEPROM布局中讨论了单级多NMOS EEPROM存储单元的阵列结构和操作该阵列的方法，其消除了使用阵列核心区域中的高压晶体管。 如果利用它们，则高压晶体管被移动到周边区域中的行和列驱动器以增加阵列密度，很少或没有附加的工艺复杂性，以允许经济地实现更大的嵌入式SLP EEPROM阵列。 在阵列的编程或擦除操作期间，该方法为阵列的所选择的存储单元提供编程电压，并向剩余的未选择的存储单元写入半写（例如，中级）电压，以避免干扰未选择的存储单元 的数组。

公开(公告)号：US07019356B2

公开(公告)日：2006-03-28

申请号：US10910210

申请日：2004-08-02

申请人： Jozef Mitros ,  Victor Ivanov

发明人： Jozef Mitros ,  Victor Ivanov

IPC分类号： H01L29/788 ,  H01L31/119 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/7883

摘要： The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second active region is formed in the second lightly doped region. A third active region is formed in the bulk substrate. An oxide layer is disposed outwardly from the bulk substrate and a floating gate layer is disposed outwardly from the oxide layer. In a particular aspect, a memory device is provided that is a single poly electrically erasable programmable read-only memory (EEPROM) with a drain or source electrode configured to remove negative charge from the gate and erase the EEPROM, without a separate erase region.

摘要翻译： 本发明提供了一种包括体基板的存储器件。 在本体衬底中形成第一轻掺杂区域。 在第一轻掺杂区域中形成第一有源区。 在本体衬底中形成第二轻掺杂区域。 在第二轻掺杂区域中形成第二有源区。 在本体衬底中形成第三有源区。 氧化物层从本体衬底向外设置，并且浮栅层从氧化物层向外设置。 在特定方面，提供了一种存储器件，其是具有漏极或源极电极的单个多电电可擦除可编程只读存储器（EEPROM），其被配置为从栅极去除负电荷并擦除EEPROM，而没有单独的擦除区域。

公开(公告)号：US07166903B2

公开(公告)日：2007-01-23

申请号：US11400464

申请日：2006-04-07

申请人： Jozef Mitros ,  Ralph Oberhuber

发明人： Jozef Mitros ,  Ralph Oberhuber

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L29/00

CPC分类号： H01L27/105 ,  H01L27/0629 ,  H01L27/0733 ,  H01L27/0805 ,  H01L27/11517 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S438/957

摘要： Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage. Other systems and methods are disclosed.

公开(公告)号：US20060022258A1

公开(公告)日：2006-02-02

申请号：US10910210

申请日：2004-08-02

申请人： Jozef Mitros ,  Victor Ivanov

发明人： Jozef Mitros ,  Victor Ivanov

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/7883

摘要： The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second active region is formed in the second lightly doped region. A third active region is formed in the bulk substrate. An oxide layer is disposed outwardly from the bulk substrate and a floating gate layer is disposed outwardly from the oxide layer. In a particular aspect, a memory device is provided that is a single poly electrically erasable programmable read-only memory (EEPROM) with a drain or source electrode configured to remove negative charge from the gate and erase the EEPROM, without a separate erase region.

摘要翻译： 本发明提供了一种包括体基板的存储器件。 在本体衬底中形成第一轻掺杂区域。 在第一轻掺杂区域中形成第一有源区。 在本体衬底中形成第二轻掺杂区域。 在第二轻掺杂区域中形成第二有源区。 在本体衬底中形成第三有源区。 氧化物层从本体衬底向外设置，并且浮栅层从氧化物层向外设置。 在特定方面，提供了一种存储器件，其是具有漏极或源极电极的单个多电电可擦除可编程只读存储器（EEPROM），其被配置为从栅极去除负电荷并擦除EEPROM，而没有单独的擦除区域。

公开(公告)号：US07498219B2

公开(公告)日：2009-03-03

申请号：US10413733

申请日：2003-04-15

申请人： Weidong Tian ,  Jozef Mitros ,  Victor Ivanov

发明人： Weidong Tian ,  Jozef Mitros ,  Victor Ivanov

IPC分类号： H01L21/8242

CPC分类号： H01L28/40 ,  H01L21/31155 ,  H01L27/0805 ,  H01L28/75

摘要： Semiconductor devices and fabrication methods are provided in which a capacitor dielectric is provided with phosphorus or other n-type dopants through implantation of other techniques to reduce the voltage coefficient of capacitance and/or the dielectric absorption of the capacitor.

摘要翻译： 提供半导体器件和制造方法，其中电容器电介质通过注入其它技术来提供磷或其它n型掺杂剂，以降低电容器的电压系数和/或电介质吸收。

公开(公告)号：US07045418B2

公开(公告)日：2006-05-16

申请号：US10387164

申请日：2003-03-12

申请人： Jozef Mitros ,  Weidong Tian ,  Pinghai Hao ,  Victor Ivanov

发明人： Jozef Mitros ,  Weidong Tian ,  Pinghai Hao ,  Victor Ivanov

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L27/11526 ,  H01L21/28194 ,  H01L27/115 ,  H01L27/11534 ,  H01L29/511 ,  H01L29/66825 ,  Y10S257/913

摘要： The present invention provides a semiconductor device (200), a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor device (200) includes a floating gate (230) located over a semiconductor substrate (210), wherein the floating gate (230) has a metal control gate (250) located thereover. The semiconductor device (200), in the same embodiment, further includes a dielectric layer (240) located between the floating gate 230 and the metal control gate (250), the dielectric layer (240) having a gettering material located therein.

摘要翻译： 本发明提供一种半导体器件（200）及其制造方法以及包括该半导体器件的集成电路。 在本发明的一个实施例中，半导体器件（200）包括位于半导体衬底（210）上的浮动栅极（230），其中浮置栅极（230）具有位于其上的金属控制栅极（250）。 在同一实施例中，半导体器件（200）还包括位于浮置栅极230和金属控制栅极（250）之间的介电层（240），介电层（240）具有位于其中的吸气材料。

公开(公告)号：US20050221595A1

公开(公告)日：2005-10-06

申请号：US11145460

申请日：2005-06-02

申请人： Imran Khan ,  Louis Hutter ,  James Todd ,  Jozef Mitros ,  William Nehrer

发明人： Imran Khan ,  Louis Hutter ,  James Todd ,  Jozef Mitros ,  William Nehrer

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L29/66825 ,  H01L21/28273

摘要： A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成氧化物层。 多晶硅层从氧化物层向外设置，其中多晶硅层形成浮栅。 PSG层从多晶硅层向外设置并平坦化。 该器件被图形蚀刻以形成电容器通道，其中电容器通道基本上设置在由多晶硅层形成的浮置栅极的上方。 在从多晶硅层向外设置的电容器通道中形成介电层。 形成可操作以充分充电电容器通道的钨插头。

公开(公告)号：US07396722B2

公开(公告)日：2008-07-08

申请号：US11347599

申请日：2006-02-03

申请人： Jozef Mitros ,  Victor Ivanov

发明人： Jozef Mitros ,  Victor Ivanov

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/7883

摘要： The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second active region is formed in the second lightly doped region. A third active region is formed in the bulk substrate. An oxide layer is disposed outwardly from the bulk substrate and a floating gate layer is disposed outwardly from the oxide layer. In a particular aspect, a memory device is provided that is a single poly electrically erasable programmable read-only memory (EEPROM) with a drain or source electrode configured to remove negative charge from the gate and erase the EEPROM, without a separate erase region.

摘要翻译： 本发明提供了一种包括体基板的存储器件。 在本体衬底中形成第一轻掺杂区域。 在第一轻掺杂区域中形成第一有源区。 在本体衬底中形成第二轻掺杂区域。 在第二轻掺杂区域中形成第二有源区。 在本体衬底中形成第三有源区。 氧化物层从本体衬底向外设置，并且浮栅层从氧化物层向外设置。 在特定方面，提供了一种存储器件，其是具有漏极或源极电极的单个多电电可擦除可编程只读存储器（EEPROM），其被配置为从栅极去除负电荷并擦除EEPROM，而没有单独的擦除区域。

公开(公告)号：US07244651B2

公开(公告)日：2007-07-17

申请号：US10442524

申请日：2003-05-21

申请人： Xiaoju Wu ,  Jozef Mitros ,  Pinghai Hao

发明人： Xiaoju Wu ,  Jozef Mitros ,  Pinghai Hao

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7838

摘要： The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the Vtp implant into a channel region of an n-well that substantially underlies a floating gate structure. The Vtp implant can be blocked by providing a mask overlying the surface of the channel region of the n-well during implantation of the Vtp implant.

摘要翻译： 可以减少使用掩埋沟道PMOS技术形成的OTP-EPROM单元的漏电流。 OTP-EPROM的漏电流的减少可以通过将V基质植入物阻挡到基本上位于浮栅结构的n阱的通道区域中来实现。 可以通过在注入植入物期间提供覆盖n阱的沟道区域的表面的掩模来阻止V >tp注入。