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公开(公告)号：US09036420B2
公开(公告)日：2015-05-19
申请号：US13471816
申请日：2012-05-15
Applicant: Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , Alexander Alexeyev , Eric Nestler , David Reynolds , William Bradley , Vladimir Zlatkovic
Inventor： Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , Alexander Alexeyev , Eric Nestler , David Reynolds , William Bradley , Vladimir Zlatkovic
CPC classification number: G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
Abstract translation: 存储装置包括具有一组存储元件的存储阵列。 每个存储元件可以写入一组离散的物理状态。 读取电路选择一个或多个存储元件，并为每个选定的存储元件生成表示所选存储元件的物理状态的模拟信号。 信号处理电路处理模拟信号以产生多个输出，其中每个输出表示所选择的存储元件与离散的物理状态集合中的一个或多个的不同子集的关联程度。
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公开(公告)号：US10739424B2
公开(公告)日：2020-08-11
申请号：US15935830
申请日：2018-03-26
Applicant: Alexander Alexeyev
Inventor： Alexander Alexeyev
Abstract: Systems and methods for reducing variability in the output impedance of an integrated switch-mode power amplifier (PA) split the output impedance between passive resistor, which may be on-chip, and a MOSFET switch of the amplifier. The PA may have a single-ended configuration or a differential configuration having two single-ended structures operating with opposite phases. In one implementation, the size of the MOSFET switch is larger than that of the MOSFET switch implemented in a conventional PA, but the size is still acceptable to operate the PA at a desired frequency. In addition, a calibration approach may be utilized to ensure that the MOSFET switch has a controlled and calibrated ON resistance, thereby providing stable output power levels of the PA and ensuring consistency and repeatability in NMR measurements.
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公开(公告)号：US09294127B2
公开(公告)日：2016-03-22
申请号：US13819360
申请日：2011-09-01
Applicant: Alexander Alexeyev
Inventor： Alexander Alexeyev
CPC classification number: H03M13/11 , G06N7/005 , H03M13/1111 , H03M13/6597
Abstract: An analog belief propagation system uses current mode implementations of storage elements and circuit implementations of at least some nodes of a factor graph using current representations. The system mitigates or avoids effects of non-linearities and approximations in storage and processing elements of the system, for instance, by using storage cells that reproduce current values and using factor circuits that separate control sections and signal path sections of the circuits.
Abstract translation: 模拟信念传播系统使用当前表示的因子图的至少一些节点的存储元件的电流模式实现和电路实现。 该系统减轻或避免了系统的存储和处理元件中的非线性和近似的影响，例如通过使用再现电流值的存储单元并且使用分离电路的控制部分和信号路径部分的因子电路。
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公开(公告)号：US08344924B2
公开(公告)日：2013-01-01
申请号：US13095188
申请日：2011-04-27
Applicant: Benjamin Vigoda , Jeffrey Bernstein , Alexander Alexeyev , William Bradley , Theophane Weber
Inventor： Benjamin Vigoda , Jeffrey Bernstein , Alexander Alexeyev , William Bradley , Theophane Weber
IPC: H03M1/12
CPC classification number: G06J1/00
Abstract: An approach to converting an analog value based on a partition of an input range produces probabilities that the input is found within each of the regions based, for example, on a noisy version of the input. In some examples, iterative and/or pipelined application of comparison circuitry is used to accumulate a set of analog representations of the output probabilities. The circuitry can be adapted or configured according to the characteristics of the degradation (e.g., according to the variance of an additive noise) and/or prior information about the distribution of the clean input (e.g., a distribution over a discrete set of exemplar values, uniformly distributed etc.).
Abstract translation: 基于输入范围的分区来转换模拟值的方法产生在例如基于输入的噪声版本的情况下在每个区域内发现输入的概率。 在一些示例中，使用比较电路的迭代和/或流水线应用来累积输出概率的一组模拟表示。 电路可以根据劣化的特性进行调整或配置（例如，根据加性噪声的变化）和/或关于干净输入分布的先前信息（例如，在离散的一组样本值上的分布 ，均匀分布等）。
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公开(公告)号：US20180275232A1
公开(公告)日：2018-09-27
申请号：US15935815
申请日：2018-03-26
Applicant: Michael Trakimas , Alexander Alexeyev
Inventor： Michael Trakimas , Alexander Alexeyev
CPC classification number: G01R33/3621 , G01R33/302 , G01R33/3607 , G01R33/3628 , G01R33/543
Abstract: Various approaches of adjusting a gain of received signals in integrated circuitry include implementing an open-loop source-degenerated amplifier having a pair of input devices for amplifying the received signals; boosting an effective transconductance of the input devices (e.g., using a pair of super-gm feedback loops); and setting a bias current of devices in the open-loop source-degenerated amplifier (e.g., using a constant-gm bias circuit.)
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Patent Agency Ranking
公开(公告)号：US08179731B2
公开(公告)日：2012-05-15
申请号：US12537045
申请日：2009-08-06
Applicant: Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Zlatkovic
Inventor： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Zlatkovic
IPC: G11C7/00
CPC classification number: G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
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公开(公告)号：US08107306B2
公开(公告)日：2012-01-31
申请号：US12537081
申请日：2009-08-06
Applicant: Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Zlatkovic
Inventor： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Zlatkovic
IPC: G11C7/00
CPC classification number: G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
Abstract translation: 存储装置包括具有一组存储元件的存储阵列。 每个存储元件可以写入一组离散的物理状态。 读取电路选择一个或多个存储元件，并为每个选定的存储元件生成表示所选存储元件的物理状态的模拟信号。 信号处理电路处理模拟信号以产生多个输出，其中每个输出表示所选择的存储元件与离散的物理状态集合中的一个或多个的不同子集的关联程度。
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公开(公告)号：US20110255612A1
公开(公告)日：2011-10-20
申请号：US13032520
申请日：2011-02-22
Applicant: Jeffrey Bernstein , Benjamin Vigoda , David Reynolds , Alexander Alexeyev , William Bradley
Inventor： Jeffrey Bernstein , Benjamin Vigoda , David Reynolds , Alexander Alexeyev , William Bradley
IPC: H04L27/00
CPC classification number: H03M13/6597 , H03M13/1111
Abstract: A processor implements a network of functional nodes and communication paths between the nodes. The processor includes a plurality of circuit implementations of the functional nodes of the processor; and a plurality of signal paths implementing the communication paths linking the circuit implementations of the nodes. At least some of the signal paths are configured to pass signal values represented according to temporal patterns of signal levels on the signal paths. The processor also includes a plurality of circuit components for conversion between a signal value represented as a signal level (e.g., voltage or current level) and a signal value represented as a temporal pattern.
Abstract translation: 处理器实现节点之间的功能节点和通信路径的网络。 处理器包括处理器的功能节点的多个电路实现; 以及实现链接节点的电路实现的通信路径的多个信号路径。 至少一些信号路径被配置为传递根据信号路径上的信号电平的时间模式表示的信号值。 处理器还包括用于在表示为信号电平（例如，电压或电流电平）的信号值和表示为时间模式的信号值之间进行转换的多个电路部件。
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公开(公告)号：US20100246287A1
公开(公告)日：2010-09-30
申请号：US12537045
申请日：2009-08-06
Applicant: Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , David Reynolds , Alexander Alexeyev
Inventor： Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , David Reynolds , Alexander Alexeyev
CPC classification number: G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
Abstract translation: 存储装置包括具有一组存储元件的存储阵列。 每个存储元件可以写入一组离散的物理状态。 读取电路选择一个或多个存储元件，并为每个选定的存储元件生成表示所选存储元件的物理状态的模拟信号。 信号处理电路处理模拟信号以产生多个输出，其中每个输出表示所选择的存储元件与离散的物理状态集合中的一个或多个的不同子集的关联程度。
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公开(公告)号：US07112990B2
公开(公告)日：2006-09-26
申请号：US10759756
申请日：2004-01-16
Applicant: Steven M. Waldstein , Maurice Richard , Alexander Alexeyev , David Reynolds
Inventor： Steven M. Waldstein , Maurice Richard , Alexander Alexeyev , David Reynolds
CPC classification number: G01R31/318558 , G01R31/318594 , H03K5/133 , H03K2005/0013
Abstract: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.
Abstract translation: 提供对物理层的改进，例如不会将关键时钟信号进一步偏移的测试电路。 还提供了用于隔离用于施加测试矢量或电路品牌连接的集成电路以测试其完整性的边界扫描测试电路。 还提供了用于电压控制延迟线（VCDL）的偏置电压发生器。
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