公开(公告)号：US07440504B2

公开(公告)日：2008-10-21

申请号：US10246977

申请日：2002-09-19

Applicant: Alexander G. Maclnnis ,  Sheng Zhong ,  Jose R. Alvarez

Inventor： Alexander G. Maclnnis ,  Sheng Zhong ,  Jose R. Alvarez

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04B1/66

CPC classification number: H04N19/86 ,  H04N19/117 ,  H04N19/159 ,  H04N19/16 ,  H04N19/176 ,  H04N19/80

Abstract: A method and apparatus are disclosed for adaptively selecting a deblocking filter used in video de-blocking. Determinations are made as to whether each of a set of spatially adjacent video blocks is inter-coded or intra-coded and whether each of said adjacent video blocks is field-coded or frame-coded. A deblocking filter is selected (an interlace deblocking filter or a frame deblocking filter) based on the determinations. The selected deblocking filter is used to filter across a boundary between adjacent video blocks.

Abstract translation: 公开了一种用于自适应地选择用于视频去阻塞中的去块滤波器的方法和装置。 确定一组空间相邻的视频块中的每一个是帧间编码还是帧内编码，以及所述相邻视频块中的每一个是场编码还是帧编码。 基于确定，选择去块滤波器（隔行去块滤波器或帧去块滤波器）。 所选择的去块滤波器用于过滤相邻视频块之间的边界。

公开(公告)号：US20120328000A1

公开(公告)日：2012-12-27

申请号：US13608192

申请日：2012-09-10

Applicant: Alexander G. MacInnis ,  Jose' R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Alexander G. MacInnis ,  Jose' R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/26

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  H04N19/91

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

Abstract translation: 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。

公开(公告)号：US08229002B2

公开(公告)日：2012-07-24

申请号：US13018840

申请日：2011-02-01

Applicant: Alexander G. MacInnis ,  Jose R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Alexander G. MacInnis ,  Jose R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/18

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  H04N19/91

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

公开(公告)号：US07630566B2

公开(公告)日：2009-12-08

申请号：US10247940

申请日：2002-09-20

Applicant: Alexander G MacInnis ,  Sheng Zhong ,  Jose R Alvarez

Inventor： Alexander G MacInnis ,  Sheng Zhong ,  Jose R Alvarez

IPC: G06K9/36 ,  G06K9/46

CPC classification number: H04N19/523 ,  G06T7/223 ,  H04N19/51 ,  H04N19/533 ,  H04N19/61 ,  H04N19/80 ,  H04N19/82

Abstract: A method and apparatus are disclosed for performing motion estimation and compensation to fractional pixel accuracy using polyphase prediction filters as part of a video compression/decompression technique. A motion estimator applies a set of polyphase filters to some data in the reference picture and generates motion vectors, an estimated macroblock of video data, and a residual error macroblock of video data. The data referenced in the reference picture usually have more data than a macroblock since multi-tap filtering needs to access more data. A motion compensator generates a compensated macroblock of video data in response to the reference video data, the residual error macroblock of video data, and a polyphase prediction filter decided by the motion vector. The reference video data are usually reconstructed at the compensator side.

Abstract translation: 公开了一种用于使用多相预测滤波器作为视频压缩/解压缩技术的一部分来执行运动估计和补偿到分数像素精度的方法和装置。 运动估计器将一组多相滤波器应用于参考图像中的一些数据，并产生运动矢量，视频数据的估计宏块和视频数据的残差误差宏块。 参考图中参考的数据通常具有比宏块更多的数据，因为多点抽头需要访问更多的数据。 运动补偿器响应于参考视频数据，视频数据的残余误差宏块和由运动矢量决定的多相预测滤波器，生成补偿的视频数据的宏块。 参考视频数据通常在补偿器一侧重建。

公开(公告)号：US09104424B2

公开(公告)日：2015-08-11

申请号：US13205776

申请日：2011-08-09

Applicant: Jose R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Jose R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/18 ,  G06F9/38 ,  H04N19/176 ,  H04N19/70 ,  H04N19/13 ,  H04N19/122 ,  H04N19/129 ,  H04N19/61 ,  H04N19/60 ,  H04N19/12 ,  H04N19/157 ,  H04N19/44 ,  H04N19/82 ,  H04N19/423 ,  H04N19/90

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/13 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.

公开(公告)号：US20110122941A1

公开(公告)日：2011-05-26

申请号：US13018840

申请日：2011-02-01

Applicant: Alexander G. MacInnis ,  Jose R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Alexander G. MacInnis ,  Jose R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/26 ,  H04N7/30

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  H04N19/91

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

Abstract translation: 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。

公开(公告)号：US07034897B2

公开(公告)日：2006-04-25

申请号：US10114679

申请日：2002-04-01

Applicant: Jose′ R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Jose′ R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/18

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/13 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.

公开(公告)号：US06963613B2

公开(公告)日：2005-11-08

申请号：US10114797

申请日：2002-04-01

Applicant: Alexander G. MacInnis ,  Vivian Hsiun ,  Sheng Zhong ,  Xiaodong Xie ,  Kimming So ,  Jose′ R. Alvarez

Inventor： Alexander G. MacInnis ,  Vivian Hsiun ,  Sheng Zhong ,  Xiaodong Xie ,  Kimming So ,  Jose′ R. Alvarez

IPC: G06F9/38 ,  G06T9/00 ,  H04N7/26 ,  H04N7/30 ,  H04N7/50 ,  H04N7/12

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/13 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90

Abstract: Means of communicating between modules in a decoding system. A variable-length decoding accelerator communicates with a core decoder processor via a co-processor interface. In one embodiment, other decoding accelerators, in addition to the variable-length decoder, are adapted to provide status data indicative of their status to a co-processor status register. In another embodiment, a decoding accelerator is controlled by providing commands to the accelerator via posted write operations and polling the accelerator to determine whether the command has been performed. In still another embodiment, a first hardware accelerator communicates with a core decoder processor via a co-processor interface and other decoding accelerators, in addition to the first hardware accelerator, are adapted to provide status data indicative of their status to a co-processor status register.

Abstract translation: 在解码系统中的模块之间进行通信的手段。 可变长度解码加速器经由协处理器接口与核心解码器处理器进行通信。 在一个实施例中，除了可变长度解码器之外，其他解码加速器适于向协处理器状态寄存器提供表示其状态的状态数据。 在另一个实施例中，解码加速器通过经由发布的写入操作向加速器提供命令并轮询加速器来控制，以确定该命令是否已被执行。 在另一个实施例中，第一硬件加速器经由协处理器接口与核心解码器处理器进行通信，并且除了第一硬件加速器之外，其他解码加速器适于将表示其状态的状态数据提供给协处理器状态 寄存器。

公开(公告)号：US09329871B2

公开(公告)日：2016-05-03

申请号：US13608192

申请日：2012-09-10

Applicant: Alexander G. MacInnis ,  Jose′ R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Alexander G. MacInnis ,  Jose′ R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/18 ,  G06F9/38 ,  H04N19/176 ,  H04N19/70 ,  H04N19/122 ,  H04N19/129 ,  H04N19/61 ,  H04N19/60 ,  H04N19/12 ,  H04N19/91 ,  H04N19/157 ,  H04N19/44 ,  H04N19/82 ,  H04N19/423 ,  H04N19/90 ,  H04N19/625

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  H04N19/91

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

公开(公告)号：US20130022105A1

公开(公告)日：2013-01-24

申请号：US13608221

申请日：2012-09-10

Applicant: Alexander G. MacInnis ,  Jose' R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Alexander G. MacInnis ,  Jose' R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/12

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  H04N19/91

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

Abstract translation: 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。