公开(公告)号：US07573516B2

公开(公告)日：2009-08-11

申请号：US10958592

申请日：2004-10-06

Applicant: Alexander I. Krymski ,  Kwang-Bo Cho

Inventor： Alexander I. Krymski ,  Kwang-Bo Cho

IPC: H04N5/335 ,  G03B7/00

CPC classification number: H04N5/3532 ,  H04N5/2353 ,  H04N5/3745 ,  H04N5/3765

Abstract: A shutter system for a pixel array is disclosed. The system includes a read shift register, first and second reset shift registers, and a plurality of logic gates. The read shift register is configured to sequentially count rows of the pixel array from top to bottom, such that the read shift register generates a read pointer. The first reset shift register is configured to sequentially reset rows of the pixel array from top to bottom. The first reset shift register provides a first reset pointer for allowing reset of pixels in a row indicated by the first reset pointer. The first reset pointer allows reset of pixels prior to reading of the pixels in a row indicated by the read pointer. The time difference between the first reset pointer and the read pointer indicates an exposure time. The second reset shift register is configured to provide a second reset pointer, which enables the first reset shift register to sequentially reset rows of the pixel array without generating any flashes when the exposure time is increased. The plurality of logic gates direct outputs of the read shift register and the first and second reset shift registers to each pixel in the pixel array.

Abstract translation: 公开了一种用于像素阵列的快门系统。 该系统包括读移位寄存器，第一和第二复位移位寄存器以及多个逻辑门。 读移位寄存器被配置为从上到下顺序地计数像素阵列的行，使得读移位寄存器生成读指针。 第一复位移位寄存器被配置为从顶部到底部依次重置像素阵列的行。 第一复位移位寄存器提供第一复位指针，用于允许由第一复位指针指示的行中的像素复位。 第一个复位指针允许在读取指针所指示的行中的像素之前复位像素。 第一复位指针和读指针之间的时间差表示曝光时间。 第二复位移位寄存器被配置为提供第二复位指针，其使第一复位移位寄存器能够在曝光时间增加时顺序地复位像素阵列的行，而不产生任何闪烁。 多个逻辑门将读取的移位寄存器和第一和第二复位移位寄存器的输出直接引导到像素阵列中的每个像素。

公开(公告)号：US06809766B1

公开(公告)日：2004-10-26

申请号：US09773400

申请日：2001-01-31

Applicant: Alexander I. Krymski ,  Kwang-Bo Cho

Inventor： Alexander I. Krymski ,  Kwang-Bo Cho

IPC: H04N5335

CPC classification number: H04N5/3532 ,  H04N5/2353 ,  H04N5/3745 ,  H04N5/3765

Abstract: A shutter system for a pixel array is disclosed. The system includes a read shift register, first and second reset shift registers, and a plurality of logic gates. The read shift register is configured to sequentially count rows of the pixel array from top to bottom, such that the read shift register generates a read pointer. The first reset shift register is configured to sequentially reset rows of the pixel array from top to bottom. The first reset shift register provides a first reset pointer for allowing reset of pixels in a row indicated by the first reset pointer. The first reset pointer allows reset of pixels prior to reading of the pixels in a row indicated by the read pointer. The time difference between the first reset pointer and the read pointer indicates an exposure time. The second reset shift register is configured to provide a second reset pointer, which enables the first reset shift register to sequentially reset rows of the pixel array without generating any flashes when the exposure time is increased. The plurality of logic gates direct outputs of the read shift register and the first and second reset shift registers to each pixels in the pixel array.

Abstract translation: 公开了一种用于像素阵列的快门系统。 该系统包括读移位寄存器，第一和第二复位移位寄存器以及多个逻辑门。 读移位寄存器被配置为从上到下顺序地计数像素阵列的行，使得读移位寄存器生成读指针。 第一复位移位寄存器被配置为从顶部到底部依次重置像素阵列的行。 第一复位移位寄存器提供第一复位指针，用于允许由第一复位指针指示的行中的像素复位。 第一个复位指针允许在读取指针所指示的行中的像素之前复位像素。 第一复位指针和读指针之间的时间差表示曝光时间。 第二复位移位寄存器被配置为提供第二复位指针，其使第一复位移位寄存器能够在曝光时间增加时顺序地复位像素阵列的行，而不产生任何闪烁。 多个逻辑门将读取移位寄存器和第一和第二复位移位寄存器的输出引导到像素阵列中的每个像素。

公开(公告)号：US20120263396A1

公开(公告)日：2012-10-18

申请号：US13473037

申请日：2012-05-16

Applicant: Kwang-Bo Cho

Inventor： Kwang-Bo Cho

IPC: G06K9/36

CPC classification number: H04N5/357 ,  H04N5/335

Abstract: A relatively non-complex signal processor supporting an active pixel sensor imaging system is disclosed. The signal processor only requires the first sample from a group of samples in a multiple sample to be transmitted to the signal processor at full resolution. The subsequent samples in that group can be transmitted using only a subset of least significant bits. The minimum number of required LSBs is based upon the level of noise in the system. In one embodiment, the number of LSBs transmitted is k+2 per sample, where k indicates the number bits corresponding to peak noise. In an alternative embodiment, each subsequent sample is transmitted using only k+1 bits.

Abstract translation: 公开了一种支持有源像素传感器成像系统的相对非复杂的信号处理器。 信号处理器仅需要多个采样中的一组采样中的第一个采样以全分辨率传输到信号处理器。 该组中的后续样本可以仅使用最低有效位的子集来传输。 所需LSB的最小数量取决于系统中的噪声水平。 在一个实施例中，每个样本发送的LSB数为k + 2，其中k表示对应于峰值噪声的数位。 在替代实施例中，每个后续采样仅使用k + 1位进行传输。

公开(公告)号：US08266818B2

公开(公告)日：2012-09-18

申请号：US11591534

申请日：2006-11-02

Applicant: Kwang-Bo Cho

Inventor： Kwang-Bo Cho

IPC: H04N9/04

CPC classification number: H04N9/045 ,  H04N2209/045

Abstract: A macro pixel is provided. The macro pixel includes at least two color pixel elements. Each color pixel element includes a photoreceptor that in response to receiving light, generates an output signal that is indicative of the quantity of light photons of a color are received. Each of the color pixel elements are configured to receive a corresponding color. The photoreceptor of each color pixel element has a geometry and a responsivity to light that is a function of the geometry of the photoreceptor such that the responsivity of the output signal of the photoreceptor to the corresponding color is controllable by changing the geometry. The geometries of the photoreceptors are selected so that a predetermined relative sensitivity to each color is obtained.

Abstract translation: 提供了一个宏像素。 宏像素包括至少两个彩色像素元件。 每个彩色像素元件包括响应于接收光的感光体，产生指示接收到颜色的光子的量的输出信号。 每个彩色像素元件被配置为接收相应的颜色。 每个彩色像素元件的感光体具有作为光感受器的几何形状的函数的光的几何形状和响应性，使得感光体的输出信号对相应颜色的响应度可通过改变几何形状来控制。 选择感光体的几何形状，使得获得对每种颜色的预定相对灵敏度。

公开(公告)号：US20110037738A1

公开(公告)日：2011-02-17

申请号：US12910215

申请日：2010-10-22

Applicant: Kwang-Bo Cho

Inventor： Kwang-Bo Cho

IPC: G06F3/038

CPC classification number: H04N5/357 ,  H04N5/335

Abstract: A relatively non-complex signal processor supporting an active pixel sensor imaging system is disclosed. The signal processor only requires the first sample from a group of samples in a multiple sample to be transmitted to the signal processor at full resolution. The subsequent samples in that group can be transmitted using only a subset of least significant bits. The minimum number of required LSBs is based upon the level of noise in the system. In one embodiment, the number of LSBs transmitted is k+2 per sample, where k indicates the number bits corresponding to peak noise. In an alternative embodiment, each subsequent sample is transmitted using only k+1 bits.

Abstract translation: 公开了一种支持有源像素传感器成像系统的相对非复杂的信号处理器。 信号处理器仅需要多个采样中的一组采样中的第一个采样以全分辨率传输到信号处理器。 该组中的后续样本可以仅使用最低有效位的子集来传输。 所需LSB的最小数量取决于系统中的噪声水平。 在一个实施例中，每个采样发送的LSB数为k + 2，其中k表示对应于峰值噪声的位数。 在替代实施例中，每个后续采样仅使用k + 1位进行发送。

公开(公告)号：US20090072899A1

公开(公告)日：2009-03-19

申请号：US12323640

申请日：2008-11-26

Applicant: Taehee Cho ,  Sandor L. Barna ,  Andrew M. Lever ,  Kwang-Bo Cho ,  Chiajen Lee

Inventor： Taehee Cho ,  Sandor L. Barna ,  Andrew M. Lever ,  Kwang-Bo Cho ,  Chiajen Lee

IPC: H03F1/08

CPC classification number: H03M1/0607 ,  H03M1/0695 ,  H03M1/1225 ,  H03M1/442

Abstract: A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is switched. The discharging act occurs when a short reset pulse is generated between two clock phases. The short reset pulse is applied to a switch connected to the operational amplifier input. When the reset pulse closes the switch, a discharge path is created and any parasitic capacitance at the operational amplifier input is discharged through the path. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.

Abstract translation: 在级/通道的放大器配置之前，在流水线模数转换器的两个级和/或两个信道处理电路之间共享的运算放大器的输入端放电寄生电容的机构被切换 。 当在两个时钟相位之间产生短暂的复位脉冲时，会发生放电动作。 短复位脉冲施加到连接到运算放大器输入的开关。 当复位脉冲闭合开关时，产生放电路径，运算放大器输入端的任何寄生电容通过路径放电。 寄生电容的放电大大减轻了存储器效应和与存储器效应相关的问题。

公开(公告)号：US07456884B2

公开(公告)日：2008-11-25

申请号：US10633673

申请日：2003-08-05

Applicant: Ilia Ovsiannikov ,  Kwang-Bo Cho ,  Michael Kaplinsky

Inventor： Ilia Ovsiannikov ,  Kwang-Bo Cho ,  Michael Kaplinsky

IPC: H04N5/335 ,  H04N5/217

CPC classification number: H04N5/35509

Abstract: An apparatus and method for measuring the breakpoint of a response curve representing the voltage output of an image array having an extended dynamic range. By flooding a light-opaque pixel with a charge and then applying an intermediate reset voltage to the pixel, the signal is read from the pixel and stored. The full reset voltage is applied to the pixel, and then the signal in the pixel is read and stored. The voltage output difference is the difference between the first and second stored signal. The voltage output difference is then used to determine the voltage of the knee point. Further, a conventional saturated pixel can be reset with an intermediate reset just prior to readout. The resulting signal can then be used to determine the voltage of the knee point.

Abstract translation: 一种用于测量表示具有扩展动态范围的图像阵列的电压输出的响应曲线的断点的装置和方法。 通过用充电填充不透明的像素，然后对像素施加中间复位电压，从像素读取信号并存储。 将全部复位电压施加到像素，然后读取并存储像素中的信号。 电压输出差是第一和第二存储信号之间的差。 然后使用电压输出差异来确定拐点的电压。 此外，传统的饱和像素可以在读出之前用中间复位来复位。 然后可以使用所得到的信号来确定拐点的电压。

公开(公告)号：US06831476B2

公开(公告)日：2004-12-14

申请号：US10747952

申请日：2003-12-31

Applicant: Kwang-Bo Cho

Inventor： Kwang-Bo Cho

IPC: G01R3126

CPC classification number: G01R31/2831

Abstract: The speed of on-chip ADC testing of image sensors is increased by testing multiple chips in parallel. A wafer typically contains many individual image sensor chips. In a parallel on-chip test procedure, power is applied to a plurality of the image sensor chips and the chips are then tested in parallel. Additional power lines may need to be added to the wafer to allow power to be supplied to a plurality of the image sensor chips at once. These power lines may be etched directly on the wafer, or a wafer master may be used to overlay the wafer with the power lines for testing purposes. Additionally, test engines may be added to the wafer map to control the overall test procedures.

Abstract translation: 图像传感器片上ADC测试的速度通过并行测试多个芯片来增加。 晶片通常包含许多单独的图像传感器芯片。 在并行片上测试程序中，对多个图像传感器芯片施加功率，然后并行测试芯片。 可能需要将另外的电源线添加到晶片，以允许立即将功率提供给多个图像传感器芯片。 这些电源线可以直接蚀刻在晶片上，或者可以使用晶片主机来覆盖晶片与电源线进行测试。 此外，可以将测试引擎添加到晶片图中以控制整体测试程序。

公开(公告)号：US20120188422A1

公开(公告)日：2012-07-26

申请号：US13071342

申请日：2011-03-24

Applicant: Kwang-Bo Cho

Inventor： Kwang-Bo Cho

IPC: H04N5/335

CPC classification number: H04N5/2258 ,  H01L27/14601 ,  H01L27/14634 ,  H01L27/14643 ,  H04N5/3696 ,  H04N5/3698 ,  H04N5/3741 ,  H04N5/376

Abstract: An integrated circuit may have rows and columns of imaging pixel arrays. Row driver circuitry and column readout circuitry may be shared between the imaging pixel arrays. Control circuit blocks may bypass inactive pixel arrays and may shift signals between different signal paths on the integrated circuit. The control circuit blocks may include synchronizing circuitry for deskewing control signals and buffer circuitry for regenerating weak signals as they are distributed across the integrated circuit. An array of lenses may be associated with the integrated circuit. The spacing between imaging pixel arrays may differ at different parts of the integrated circuit. Images from multiple image sensor pixel arrays may be combined to form a single digital image. Image sensors may be provided with unique lenses, different color responses, different image pixels, different image pixel patterns, and other differences. Reference pixels may be interposed in the gaps between image sensor arrays.

Abstract translation: 集成电路可以具有成像像素阵列的行和列。 行驱动器电路和列读出电路可以在成像像素阵列之间共享。 控制电路块可以绕过非活动像素阵列并且可以在集成电路上的不同信号路径之间移位信号。 控制电路块可以包括用于去偏移控制信号的同步电路和用于在分布在集成电路上的弱信号时再生弱信号的缓冲电路。 透镜阵列可以与集成电路相关联。 成像像素阵列之间的间距在集成电路的不同部分可能不同。 来自多个图像传感器像素阵列的图像可以被组合以形成单个数字图像。 图像传感器可以具有独特的透镜，不同的颜色响应，不同的图像像素，不同的图像像素图案以及其他差异。 参考像素可以插入在图像传感器阵列之间的间隙中。

公开(公告)号：US20090201425A1

公开(公告)日：2009-08-13

申请号：US12188063

申请日：2008-08-07

Applicant: Kwang-Bo Cho

Inventor： Kwang-Bo Cho

IPC: H03M1/12

CPC classification number: H04N5/357 ,  H04N5/335

Abstract: A relatively non-complex signal processor supporting an active pixel sensor imaging system is disclosed. The signal processor only requires the first sample from a group of samples in a multiple sample to be transmitted to the signal processor at full resolution. The subsequent samples in that group can be transmitted using only a subset of least significant bits. The minimum number of required LSBs is based upon the level of noise in the system. In one embodiment, the number of LSBs transmitted is k+2 per sample, where k indicates the number bits corresponding to peak noise. In an alternative embodiment, each subsequent sample is transmitted using only k+1 bits.

Abstract translation: 公开了一种支持有源像素传感器成像系统的相对非复杂的信号处理器。 信号处理器仅需要多个采样中的一组采样中的第一个采样以全分辨率传输到信号处理器。 该组中的后续样本可以仅使用最低有效位的子集来传输。 所需LSB的最小数量取决于系统中的噪声水平。 在一个实施例中，每个采样发送的LSB数为k + 2，其中k表示对应于峰值噪声的位数。 在替代实施例中，每个后续采样仅使用k + 1位进行发送。