公开(公告)号：US06344417B1

公开(公告)日：2002-02-05

申请号：US09634444

申请日：2000-08-08

Applicant: Alexander Usenko

Inventor： Alexander Usenko

IPC: H01L21302

CPC classification number: G01P15/0922 ,  B81C1/00484 ,  B81C1/00507 ,  B81C2201/0192 ,  G01P15/0802

Abstract: A method for fabricating MEMS wherein a structural member is released without using a sacrificial layer. In one embodiment, the method comprises forming a buried hydrogen-rich layer in a semiconductor substrate, defining a release structure in the semiconductor substrate above the buried hydrogen-rich layer, and separating at least a portion of the release structure from the semiconductor substrate by cleaving the semiconductor substrate at the buried hydrogen-rich layer. The method can be used to fabricate hybrid devices wherein a MEMS device and a semiconductor device are formed on the same chip.

Abstract translation: 一种用于制造MEMS的方法，其中结构构件在不使用牺牲层的情况下被释放。 在一个实施例中，该方法包括在半导体衬底中形成埋藏的富氢层，在掩埋富氢层之上的半导体衬底中限定释放结构，并通过以下步骤将至少一部分释放结构与半导体衬底分离： 在埋藏的富氢层处切割半导体衬底。 该方法可用于制造其中MEMS器件和半导体器件形成在同一芯片上的混合器件。

公开(公告)号：US20230086715A1

公开(公告)日：2023-03-23

申请号：US17946022

申请日：2022-09-15

Applicant: Alexander Usenko

Inventor： Alexander Usenko

IPC: H01L29/861 ,  H01L29/66

Abstract: Process flow for a stacked power diode and design of the resulting diode is disclosed. Blanket epitaxy over heavy doped wafers is performed. By controlling dopant addition during epitaxy, desired n-type, diode base, and p-type doping profiles and thicknesses achieved. V-groove pattern if formed on wafers by depositing mask film, lithography and anisotropic etch. Islands surrounded by V-grooves define individual diodes. V-grooves serve as side insulation. Next, oxidation step passivates V-grooves. Further, the mask film is stripped to open diode contact areas on both sides of wafers. Next high melting point metal and low melting point metal films are selectively electroplated on all open silicon surfaces. Stacking is performed on wafer level by bonding of desired wafer count by solid-liquid interdiffusion process. Wafer stacks are sawed into individual stacked diode dies along outer slopes of V-grooves. Final stacked devices can be used as DSRD—drift step recovery diodes. Compared to DSRDs made by known methods, better fabrication yield and higher pulse power electrical performance is achieved.

公开(公告)号：US20130320404A1

公开(公告)日：2013-12-05

申请号：US13484542

申请日：2012-05-31

Applicant: Alexander Usenko

Inventor： Alexander Usenko

IPC: H01L21/30 ,  H01L29/267

CPC classification number: H01L33/0079 ,  H01L21/02252 ,  H01L21/306 ,  H01L21/76254 ,  H01L29/267 ,  H01L33/007 ,  H01L33/02 ,  H01L51/56

Abstract: A direct wafer bonding process for joining GaN and silicon substrates involves pre-treating each of the wafers in an ammonia plasma in order to render the respective contact surfaces ammophilic. The GaN substrate and the silicon substrate may each comprise single crystal wafers. The resulting hybrid semiconductor structure can be used to form high quality, low cost LEDs.

Abstract translation: 用于接合GaN和硅衬底的直接晶片接合工艺涉及对氨等离子体中的每个晶片进行预处理，以使相应的接触表面具有亲水性。 GaN衬底和硅衬底可以各自包括单晶晶片。 所得到的混合半导体结构可用于形成高质量，低成本的LED。

公开(公告)号：US06696352B1

公开(公告)日：2004-02-24

申请号：US10202566

申请日：2002-07-24

Applicant: William Carr ,  Alexander Usenko

Inventor： William Carr ,  Alexander Usenko

IPC: H01L2130

CPC classification number: H01L21/76254 ,  B81C1/00357 ,  B81C2201/019

Abstract: A process for producing a multilayered substrate. In a first step, an adhesive layer is applied to a surface of a support substrate. Then a device substrate is placed into contact with the adhesive surface. Then the adhesive is cured. Then the device substrate is thinned. The device substrate has a hydrogen trap layer inside. The trap layer is formed by ion implantation through a face surface of the device substrate. The adhesive is chosen from compounds that release hydrogen upon curing. Thinning of the device substrate is performed by cleavage along a fragile layer of hydrogen microbubbles. The microbubble layer is formed through gettering of hydrogen released from the adhesive layer upon curing onto the trap layer and evolving the trapped hydrogen into the microbubbles. The substrates are preferably silicon single crystalline wafers and the adhesive is preferably hydrogen-silsesquioxane. The process is preferentially used to manufacture silicon-on-adhesive wafers for microelectromechanical systems, multilayer CMOS, and optoelectronic applications. The layered wafers have one or more thin single crystalline device layers and one or more sacrificial/spacer layer.

Abstract translation: 一种多层基板的制造方法。 在第一步骤中，将粘合剂层施加到支撑基板的表面上。 然后将器件衬底放置成与粘合剂表面接触。 然后粘合剂固化。 然后将器件衬底减薄。 器件基板内部具有氢阱层。 陷阱层通过离子注入通过器件衬底的表面形成。 粘合剂选自固化后释放氢的化合物。 通过沿脆性层的氢气微泡进行切割来进行器件衬底的变薄。 通过在固化到捕获层上时从吸附剂层中释放的氢气吸收而形成微泡层，并将捕获的氢气放出到微泡中。 基底优选为硅单晶晶片，并且粘合剂优选为氢硅倍半氧烷。 该方法优选用于制造用于微机电系统，多层CMOS和光电应用的硅粘合剂晶片。 层状晶片具有一个或多个薄单晶器件层和一个或多个牺牲/间隔层。

公开(公告)号：US06861320B1

公开(公告)日：2005-03-01

申请号：US10406868

申请日：2003-04-04

Applicant: Alexander Usenko

Inventor： Alexander Usenko

IPC: H01L21/762 ,  H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78603 ,  H01L21/76243

Abstract: The invention provides a method of making silicon-on-insulator SOI substrates with nitride buried insulator layer by implantation of molecular deuterated ammonia ions ND3+, instead of implanting nitrogen ions (N+, or N2+) as is done in prior art nitride SOI processes. The resultant structure, after annealing, has a buried insulator with a defect density which is substantially lower than in prior art nitride SOI. The deuterated nitride SOI substrates allow much better heat dissipation than SOI with a silicon dioxide buried insulator. These substrates can be used for manufacturing of high speed and high power dissipation monolithic integrated circuits.

Abstract translation: 本发明提供了通过注入分子氘化氨离子ND3 +来制造具有氮化物掩埋绝缘体层的绝缘体上硅SOI衬底的方法，而不是像以前那样植入氮离子（N +或N 2 +） 在现有技术的氮化物SOI工艺中完成。 所得到的结构在退火之后具有埋入式绝缘体，其缺陷密度远低于现有技术的氮化物SOI。 氘代氮化物SOI衬底允许比具有二氧化硅掩埋绝缘体的SOI更好的散热。 这些基板可用于制造高速和高功率耗散的单片集成电路。

公开(公告)号：US06806171B1

公开(公告)日：2004-10-19

申请号：US10213593

申请日：2002-08-07

Applicant: Alexander Ulyashin ,  Alexander Usenko

Inventor： Alexander Ulyashin ,  Alexander Usenko

IPC: H01L2120

CPC classification number: H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/76259 ,  Y10S438/96

Abstract: A technique for forming a film of crystalline material, preferably silicon. The technique creates a sandwich structure with a weakened region at a selected depth underneath the surface. The weakened region is a layer of porous silicon with high porosity. The high porosity enclosed layer is formed by (1) forming a porous silicon layer with low porosity on surface of the substrate, (2) epitaxial growth of a non-porous layer over the low-porous layer (3) increasing of porosity of the low-porous layer making the said layer hi-porous, (4) cleaving the semiconductor substrate at said high porous layer. The porosity of the buried low-porous layer is increased by hydrogenation techniques, for example, by processing in hydrogen plasma. The process is preferentially used to produce silicon-on-insulator wafers.

Abstract translation: 用于形成结晶材料的膜，优选硅的技术。 该技术在表面下方的选定深度产生具有弱化区域的夹层结构。 弱化区域是具有高孔隙率的多孔硅层。 高孔隙率封闭层通过以下方式形成：（1）在衬底的表面上形成具有低孔隙率的多孔硅层，（2）在低孔层（3）上的无孔层的外延生长增加孔隙率 使所述层高分子化的多孔层，（4）在所述高多孔层处切割半导体衬底。 通过加氢技术，例如通过在氢等离子体中加工，增加了掩埋的低孔层的孔隙率。 该方法优选用于制造绝缘体上硅晶片。

公开(公告)号：US08796054B2

公开(公告)日：2014-08-05

申请号：US13484542

申请日：2012-05-31

Applicant: Alexander Usenko

Inventor： Alexander Usenko

IPC: H01L21/00 ,  H01L33/00 ,  H01L51/56 ,  H01L21/02

CPC classification number: H01L33/0079 ,  H01L21/02252 ,  H01L21/306 ,  H01L21/76254 ,  H01L29/267 ,  H01L33/007 ,  H01L33/02 ,  H01L51/56

Abstract: A direct wafer bonding process for joining GaN and silicon substrates involves pre-treating each of the wafers in an ammonia plasma in order to render the respective contact surfaces ammophilic. The GaN substrate and the silicon substrate may each comprise single crystal wafers. The resulting hybrid semiconductor structure can be used to form high quality, low cost LEDs.

Abstract translation: 用于接合GaN和硅衬底的直接晶片接合工艺涉及对氨等离子体中的每个晶片进行预处理，以使相应的接触表面具有亲水性。 GaN衬底和硅衬底可以各自包括单晶晶片。 所得到的混合半导体结构可用于形成高质量，低成本的LED。

公开(公告)号：US06995075B1

公开(公告)日：2006-02-07

申请号：US10195045

申请日：2002-07-12

Applicant: Alexander Usenko

Inventor： Alexander Usenko

IPC: H01L21/30

CPC classification number: H01L21/3003 ,  H01L21/26506 ,  H01L21/76254

Abstract: Process for forming a fragile layer inside of a single crystalline substrate near one of the substrate surfaces. The fragile layer contains hydrogen mostly in form of hydrogen platelets oriented in parallel to each other and to neighboring crystal surface. The fragile layer is preferably grown within a single crystalline silicon wafer to facilitate the detachment of an overlaying thin layer of single crystalline silicon from the initial wafer. The hydrogen layer is grown on a seed layer. The seed layer is preferably formed by ion implantation of inert gases at doses in 1015 cm−2 range. The hydrogen layer is grown by plasma hydrogenation of the substrate. The hydrogenation process begins at substrate temperature not exceeding 250° C., and than continues at higher temperature not exceeding 400° C. The method can be used to fabricate silicon-on-insulator (SOI) wafers wherein a thin layer of single crystalline silicon is detached from a silicon substrate along the fragile layer and attached to a substrate with an insulator on top of that substrate.

Abstract translation: 在单个基板的一个基板表面附近形成脆性层的工艺。 易碎层包含大部分氢平板形式的氢，彼此平行且相邻的晶体表面。 脆性层优选在单晶硅晶片内生长，以便于从初始晶片分离单晶硅的覆盖薄层。 氢层在种子层上生长。 种子层优选通过以10-15cm -2 -2范围的剂量离子注入惰性气体形成。 通过基板的等离子体氢化生长氢层。 氢化过程从不超过250℃的衬底温度开始，并且在不超过400℃的较高温度下继续进行。该方法可用于制造绝缘体上硅（SOI）晶片，其中单晶硅薄层 沿着脆弱层从硅衬底分离，并且在该衬底的顶部上附着到具有绝缘体的衬底上。