公开(公告)号：US06261960B1

公开(公告)日：2001-07-17

申请号：US09545698

申请日：2000-04-06

申请人： Allen S. Yu ,  Bharath Rangarajan ,  Paul J. Steffan

发明人： Allen S. Yu ,  Bharath Rangarajan ,  Paul J. Steffan

IPC分类号： H01L2100

CPC分类号： H01L21/76816 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device having rectangular cross-sectional interfaces between a conductive line and a conductive via. A first layer of photoresist is patterned to expose portions of the semiconductor device under which conductive wires and combination conductive wires and vias are to be formed. A second layer of photoresist is patterned to expose portions of the semiconductor device under which combination conductive wires and vias are to be formed. A second layer of interlayer dielectric in which conductive wires are to be formed and a first layer of interlayer dielectric in which conductive vias are to be formed are simultaneously anisotropically etched to form cavities, which are simultaneously filled with a conductive material.

摘要翻译： 一种制造在导线和导电通孔之间具有矩形截面界面的半导体器件的方法。 对第一层光致抗蚀剂进行图案化以暴露将要形成导线和组合导线和通孔的半导体器件的部分。 对第二层光致抗蚀剂进行图案化以暴露将要形成组合导线和通孔的半导体器件的部分。 要形成导线的第二层层间电介质和要形成导电通孔的第一层间电介质同时被各向异性地蚀刻以形成同时填充有导电材料的空腔。

公开(公告)号：US06191036B1

公开(公告)日：2001-02-20

申请号：US09290354

申请日：1999-04-12

申请人： Allen S. Yu ,  Paul J. Steffan ,  Bharath Rangarajan

发明人： Allen S. Yu ,  Paul J. Steffan ,  Bharath Rangarajan

IPC分类号： H01L21302

CPC分类号： G03F7/70625 ,  G03F7/70641 ,  H01L21/76802 ,  H01L22/34

摘要： A method of predicting etch efficacy of vias in a semiconductor manufacturing process wherein a photo focus exposure matrix (FEM) array is used as a via etch monitor. The FEM is an array of matrices wherein each array has a different size set of vias. The matrices in the array start with a size approximately double the minimum dimension of vias in the wafer and decrement in size to a size approximately half the minimum dimension.

摘要翻译： 在半导体制造工艺中预测通孔的蚀刻效能的方法，其中使用光焦点曝光矩阵（FEM）阵列作为通孔蚀刻监视器。 FEM是矩阵阵列，其中每个阵列具有不同大小的通孔集合。 阵列中的矩阵的大小大约是晶片中通孔的最小尺寸的两倍，尺寸减小到最小尺寸的一半左右。

公开(公告)号：US06426301B1

公开(公告)日：2002-07-30

申请号：US09628822

申请日：2000-07-31

申请人： Jeffrey A. Shields ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Allen S. Yu

发明人： Jeffrey A. Shields ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Allen S. Yu

IPC分类号： H01L21302

CPC分类号： H01L21/31144 ,  H01L21/743 ,  H01L21/76802

摘要： A wafer having a substrate and an insulating layer over the substrate that includes a conductive layer over the insulating layer. The conductive layer mitigates charges formed on a photoresist layer during etching of features (e.g., vias and trenches). Any conductive material may serve this purpose. For example, aluminum, tantalum nitride, titanium and titanium nitride. Typically, a plasma etcher is employed for forming vias and trenches in an insulating layer to create contacts and conducting lines used to connect devices residing within different layers. The plasma etcher causes charge buildup on a photoresist layer that is utilized during the etching process. The charge buildup causes potential differences on the photoresist layer, which can lead to eventual damage of devices. A conductive layer eliminates this potential differences because a charge equilibrium is established due to the conductivity of the conductive layer.

摘要翻译： 一种晶片，具有衬底和绝缘层，该衬底包括在该绝缘层上的导电层。 在蚀刻特征（例如通孔和沟槽）期间，导电层减轻在光致抗蚀剂层上形成的电荷。 任何导电材料都可以用于此目的。 例如，铝，氮化钽，钛和氮化钛。 通常，等离子体蚀刻器用于在绝缘层中形成通路和沟槽以产生用于连接驻留在不同层内的器件的触点和导线。 等离子体蚀刻器在蚀刻过程中利用的光致​​抗蚀剂层上引起电荷积聚。 电荷积聚导致光致抗蚀剂层上的电位差，这可能导致器件的最终损坏。 导电层消除了这种电位差，因为由于导电层的导电性而建立了电荷平衡。

公开(公告)号：US07065427B1

公开(公告)日：2006-06-20

申请号：US10979367

申请日：2004-11-01

申请人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Khoi A. Phan

发明人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Khoi A. Phan

IPC分类号： G06F19/00 ,  G02B7/00 ,  H01L21/00

CPC分类号： G03F7/7085 ,  G03F7/70341 ,  G03F7/70591

摘要： A multi-layer immersion medium monitoring system for a lithographic process monitors characteristics of an immersion medium of a semiconductor manufacturing process. The multi-layer immersion medium includes at least a first liquid of a first density (or viscosity) and a second liquid of a lower density (or viscosity), both of which are interspersed between a final optical component and a semiconductor layer. The higher density layer is provided to reduce turbulence in the immersion medium during the lithographic processes. A scatterometry system monitors optical characteristics of the multi-layer immersion medium to effectuate control of a lithographic process.

摘要翻译： 用于光刻工艺的多层浸渍介质监测系统监测半导体制造工艺的浸渍介质的特性。 多层浸渍介质至少包括第一密度（或粘度）的第一液体和较低密度（或粘度）的第二液体，它们都分散在最终的光学部件和半导体层之间。 提供更高密度的层以在光刻过程中减少浸没介质中的湍流。 散射测量系统监测多层浸没介质的光学特性，以实现光刻工艺的控制。

公开(公告)号：US06982043B1

公开(公告)日：2006-01-03

申请号：US10382181

申请日：2003-03-05

申请人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Catherine B. Labelle ,  Bhanwar Singh ,  Christopher F. Lyons

发明人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Catherine B. Labelle ,  Bhanwar Singh ,  Christopher F. Lyons

IPC分类号： B44C1/22

CPC分类号： H01L22/12 ,  H01L22/26

摘要： Disclosed are a system and method for monitoring a patterned photoresist clad-wafer structure undergoing an etch process. The system includes a semiconductor wafer structure comprising a substrate, one or more intermediate layers overlying the substrate, and a first patterned photoresist layer overlying the intermediate layers, the semiconductor wafer structure being etched through one or more openings in the photoresist layer; a wafer-etch photoresist monitoring system programmed to obtain data relating to the photoresist layer as the etch process progresses; a pattern-specific grating aligned with the wafer structure and employed in conjunction with the monitoring system, the grating having at least one of a pitch and a critical dimension identical to the first patterned photoresist layer; and a wafer processing controller operatively connected to the monitoring system and adapted to receive data from the monitoring system in order to determine adjustments to a subsequent wafer clean process.

摘要翻译： 公开了用于监测经历蚀刻工艺的图案化光致抗蚀剂包覆晶片结构的系统和方法。 该系统包括半导体晶片结构，其包括衬底，覆盖衬底的一个或多个中间层和覆盖中间层的第一图案化光致抗蚀剂层，半导体晶片结构通过光致抗蚀剂层中的一个或多个开口进行蚀刻; 晶片蚀刻光刻胶监测系统被编程为随着蚀刻工艺的进行获得与光致抗蚀剂层有关的数据; 与晶片结构对准并与监视系统结合使用的图案特定光栅，光栅具有与第一图案化光致抗蚀剂层相同的间距和临界尺寸中的至少一个; 以及晶片处理控制器，可操作地连接到所述监控系统并且适于从所述监控系统接收数据，以便确定随后的晶片清洁过程的调整。

公开(公告)号：US06954678B1

公开(公告)日：2005-10-11

申请号：US10261650

申请日：2002-09-30

申请人： Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

发明人： Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

IPC分类号： G01R31/26 ,  G05B23/02 ,  G06F19/00 ,  H01L21/66

CPC分类号： H01L22/26 ,  G05B23/0286

摘要： A system and method facilitating lithography defect solution generation is provided. The invention includes a defect solution component and a defect alert component. The defect solution component provides potential solution(s) to a defect within the lithography process utilizing artificial intelligence technique(s) (e.g., Bayesian learning methods that perform analysis over alternative dependent structures and apply a score, Bayesian classifiers and other statistical classifiers, including decision tree learning methods, support vector machines, linear and non-linear regression and/or neural network).

摘要翻译： 提供了一种促进光刻缺陷解决方案生成的系统和方法。 本发明包括缺陷解决方案组件和缺陷警报组件。 缺陷解决方案组件使用人工智能技术（例如，贝叶斯学习方法对替代依赖结构进行分析并应用分数贝叶斯分类器和其他统计分类器，包括 决策树学习方法，支持向量机，线性和非线性回归和/或神经网络）。

公开(公告)号：US06905950B2

公开(公告)日：2005-06-14

申请号：US09893198

申请日：2001-06-27

申请人： Ramkumar Subramanian ,  Michael K. Templeton ,  Bhanwar Singh ,  Bharath Rangarajan

发明人： Ramkumar Subramanian ,  Michael K. Templeton ,  Bhanwar Singh ,  Bharath Rangarajan

IPC分类号： H01L21/768 ,  H01L21/3205

CPC分类号： H01L21/76885 ,  H01L21/76879

摘要： The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown within the openings in a patterned coating. The patterned coating can be a resist coating or a dielectric coating. Either type of coating can be formed over a copper seed layer, whereby the seed layer is exposed within the pattern gaps. The copper seed layer can also be provided within the pattern gaps after patterning. Copper features are grown within the pattern gaps by plating. Where the patterned coating is a resist, the resist is stripped leaving the copper features in the inverse pattern image. The copper features can be coated with a diffusion barrier layer and a dielectric. The dielectric is polished to leave the dielectric filling the spaces between copper features. The invention provides copper lines and vias without the need for a dielectric or metal etching step. Another benefit of the invention is that lines widths can be increased by trimming the patterned coating prior to growing the copper features.

摘要翻译： 本发明涉及制造互连线和通孔的方法。 根据本发明，铜在图案化涂层的开口内生长。 图案化的涂层可以是抗蚀剂涂层或介电涂层。 任何一种类型的涂层可以在铜籽晶层上形成，从而种子层在图案间隙内露出。 图案化之后也可以在图案间隙内提供铜籽晶层。 铜特征通过电镀在图案间隙内生长。 在图案涂层是抗蚀剂的情况下，剥离抗蚀剂，留下逆向图案图案中的铜特征。 铜的特征可以涂覆有扩散阻挡层和电介质。 电介质被抛光以留下电介质填充铜特征之间的空间。 本发明提供铜线和通孔，而不需要电介质或金属蚀刻步骤。 本发明的另一个好处是通过在生长铜特征之前修整图案化涂层可以增加线宽。

公开(公告)号：US06879051B1

公开(公告)日：2005-04-12

申请号：US10050454

申请日：2002-01-16

申请人： Bhanwar Singh ,  Michael K. Templeton ,  Bharath Rangarajan ,  Ramkumar Subramanian

发明人： Bhanwar Singh ,  Michael K. Templeton ,  Bharath Rangarajan ,  Ramkumar Subramanian

IPC分类号： C23C16/04 ,  C23C16/52 ,  H01L21/31

CPC分类号： C23C16/045 ,  C23C16/52

摘要： One aspect of the present invention relates to a method to facilitate formation of seed layer portions on sidewall surfaces of a trench formed in a substrate. The method involves the steps of forming a conformal seed layer over a barrier layer disposed conformal to a trench, wherein the trench is formed in the substrate; reflecting a light beam of x-ray radiation at the seed layer sidewall portions; generating a measurement signal based on the reflected portion of the light beam; and determining a thickness of the sidewall portions based on the measurement signal while the sidewall portions are being formed over the trench.

摘要翻译： 本发明的一个方面涉及一种促进在衬底中形成的沟槽的侧壁表面上形成种子层部分的方法。 该方法包括以下步骤：在与沟槽共形设置的阻挡层上形成保形种子层，其中沟槽形成在衬底中; 在种子层侧壁部分反射x射线辐射的光束; 基于所述光束的反射部分生成测量信号; 以及当在所述沟槽上形成所述侧壁部分时，基于所述测量信号来确定所述侧壁部分的厚度。

公开(公告)号：US06771356B1

公开(公告)日：2004-08-03

申请号：US10050626

申请日：2002-01-16

申请人： Christopher F. Lyons ,  Bhanwar Singh ,  Steven C. Avanzino ,  Khoi A. Phan ,  Bharath Rangarajan ,  Ramkumar Subramanian ,  Cyrus E. Tabery

发明人： Christopher F. Lyons ,  Bhanwar Singh ,  Steven C. Avanzino ,  Khoi A. Phan ,  Bharath Rangarajan ,  Ramkumar Subramanian ,  Cyrus E. Tabery

IPC分类号： G01B1116

CPC分类号： G01B11/165

摘要： A system for monitoring a fabrication process is provided. The system includes one or more light sources, each light source directing light to one or more gratings on a wafer. Light reflected from the gratings is collected by a measuring system that processes the collected light. The collected light is indicative of distortion due to stress at respective portions of the wafer. The measuring system provides distortion/stress related data to a processor that determines the acceptability of the distortion of the respective portions of the wafer. The collected light may be analyzed by scatterometry systems to produce scatterometry signatures associated with distortion and to produce feed-forward control information that can be employed to control semiconductor fabrication processes.

摘要翻译： 提供了一种用于监视制造工艺的系统。 该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个光栅。 从光栅反射的光被处理收集的光的测量系统收集。 所收集的光指示由于晶片的各个部分处的应力引起的变形。 测量系统向处理器提供失真/应力相关数据，该处理器确定晶片各部分的失真的可接受性。 收集的光可以通过散射测量系统进行分析，以产生与失真相关联的散射仪签名并产生可用于控制半导体制造过程的前馈控制信息。

公开(公告)号：US06704101B1

公开(公告)日：2004-03-09

申请号：US10050423

申请日：2002-01-16

申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian ,  Michael K. Templeton

发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian ,  Michael K. Templeton

IPC分类号： G01N2100

CPC分类号： G01N21/47 ,  G01N21/4788 ,  G01N21/55 ,  G01N21/9501 ,  G01N2201/10

摘要： A system and method are disclosed for monitoring characteristics of a substrate. A substrate is supported for movement within a processing environment and an incident light beam is emitted onto a surface of the substrate. The incident beam is provided to a moveable reflector that directs the beam to the substrate. A control system controls movement of the reflector so as to selectively interrogates the substrate with the beam.

摘要翻译： 公开了用于监测基板的特性的系统和方法。 支撑衬底在处理环境中移动，并且将入射光束发射到衬底的表面上。 入射光束被提供到将光束引导到衬底的可移动反射器。 控制系统控制反射器的运动，以便选择性地用光束询问衬底。