公开(公告)号：US09501606B2

公开(公告)日：2016-11-22

申请号：US14582984

申请日：2014-12-24

申请人： Altera Corporation

发明人： Steven Teig ,  Andrew Caldwell

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5031 ,  G06F17/505 ,  G06F2217/84

摘要： A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of nodes representing IC components. The method identifies several paths in the graph that each starts from a timed source node and ends to a timed target node. Each path includes several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to one or more clocked elements to satisfy a set of timing constraints. For each identified path, the method determines the ratio of signal travel time from the source node to the destination node to a maximum time allocated for the data signal to travel from the source node to the target node. When the IC design fails timing constraints, the path that has a maximum determined ratio as a cause for timing failure.

摘要翻译： 提供了一种优化IC设计的时序性能的方法。 IC设计表示为包括表示IC组件的多个节点的图形。 该方法识别图中的多个路径，每个路径从定时源节点开始，并结束到定时目标节点。 每个路径包括几个时钟元素和几个计算元素。 该方法通过将时钟信号偏移到一个或多个时钟元件来优化IC设计的定时性能，以满足一组时序约束。 对于每个识别的路径，该方法确定从源节点到目的地节点的信号行进时间与分配用于从源节点到目标节点行进的数据信号的最大时间的比率。 当IC设计失败时序约束时，将具有最大确定比例的路径作为定时故障的原因。

公开(公告)号：US09436565B2

公开(公告)日：2016-09-06

申请号：US14281219

申请日：2014-05-19

申请人： Altera Corporation

发明人： Andrea Olgiati ,  Matthew Pond Baker ,  Steven Teig

IPC分类号： H03K19/173 ,  G06F11/263 ,  H03K19/177 ,  G06F11/22 ,  G06F11/34 ,  G06F17/50 ,  G01R31/3185

CPC分类号： G06F11/263 ,  G01R31/2851 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/079 ,  G06F11/2205 ,  G06F11/3003 ,  G06F11/3409 ,  G06F11/3466 ,  G06F17/5027 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2201/86 ,  H03K19/17756

摘要： An application-specific integrated circuit (ASIC) is provided. The ASIC includes a group of non-configurable circuits customized for performing operations for a particular use. The ASIC also includes a set of reconfigurable circuits for configurably performing a set of operations based on configuration data. The ASIC also includes a configuration and monitoring network that receives a set of signals from the non-configurable circuits of the ASIC. The configuration and monitoring network also receives incremental sets of configuration data while the ASIC is performing operations of the user design. Each incremental set of data is used for reconfiguring the configuration and monitoring network (i) to monitor one or more signals in the set of signals and (ii) to take a set of actions when values of the monitored signals satisfy a condition.

摘要翻译： 提供专用集成电路（ASIC）。 ASIC包括为特定用途执行操作而定制的一组不可配置电路。 ASIC还包括一组用于可配置地基于配置数据执行一组操作的可重新配置电路。 ASIC还包括从ASIC的不可配置电路接收一组信号的配置和监控网络。 当ASIC正在执行用户设计的操作时，配置和监视网络还接收增量的配置数据集。 每个增量数据集用于重新配置和监视网络（i）以监视该组信号中的一个或多个信号，以及（ii）当所监视的信号的值满足条件时采取一组动作。

公开(公告)号：US20150324513A1

公开(公告)日：2015-11-12

申请号：US14582984

申请日：2014-12-24

申请人： Altera Corporation

发明人： Steven Teig ,  Andrew Caldwell

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5031 ,  G06F17/505 ,  G06F2217/84

摘要： A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of nodes representing IC components. The method identifies several paths in the graph that each starts from a timed source node and ends to a timed target node. Each path includes several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to one or more clocked elements to satisfy a set of timing constraints. For each identified path, the method determines the ratio of signal travel time from the source node to the destination node to a maximum time allocated for the data signal to travel from the source node to the target node. When the IC design fails timing constraints, the path that has a maximum determined ratio as a cause for timing failure.

摘要翻译： 提供了一种优化IC设计的时序性能的方法。 IC设计表示为包括表示IC组件的多个节点的图形。 该方法识别图中的多个路径，每个路径从定时源节点开始，并结束到定时目标节点。 每个路径包括几个时钟元素和几个计算元素。 该方法通过将时钟信号偏移到一个或多个时钟元件来优化IC设计的定时性能，以满足一组时序约束。 对于每个识别的路径，该方法确定从源节点到目的地节点的信号行进时间与分配用于从源节点到目标节点行进的数据信号的最大时间的比率。 当IC设计失败时序约束时，将具有最大确定比例的路径作为定时故障的原因。

公开(公告)号：US09154134B2

公开(公告)日：2015-10-06

申请号：US14281775

申请日：2014-05-19

申请人： Altera Corporation

发明人： Martin Voogel ,  Steven Teig ,  Thomas S. Chanack ,  Andrew Caldwell ,  Jung Ko ,  Trevis Chandler

IPC分类号： H03K19/177 ,  H01L25/00 ,  H03K19/0185

CPC分类号： H03K19/177 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/018585 ,  H03K19/17704 ,  H03K19/17744 ,  H03K19/17748 ,  H03K19/1776 ,  H01L2924/00014 ,  H01L2924/00

摘要： Some embodiments provide a configurable integrated circuit (IC) having a routing fabric that includes configurable storage element in its routing fabric. In some embodiments, the configurable storage element includes a parallel distributed path for configurably providing a pair of transparent storage elements. The pair of configurable storage elements can configurably act either as non-transparent (i.e., clocked) storage elements or transparent configurable storage elements. In some embodiments, the configurable storage element in the routing fabric performs both routing and storage operations by a parallel distributed path that includes a clocked storage element and a bypass connection. In some embodiments, the configurable storage element perform both routing and storage operations by a pair of master-slave latches but without a bypass connection. The routing fabric in some embodiments supports the borrowing of time from one clock cycle to another clock cycle by using the configurable storage element that can be configure to perform both routing and storage operations in different clock cycles. In some embodiments, the routing fabric provide a low power configurable storage element that includes multiple storage elements that operates at different phases of a slower running clock.

摘要翻译： 一些实施例提供了一种具有路由结构的可配置集成电路（IC），该路由结构在其路由结构中包括可配置的存储元件。 在一些实施例中，可配置存储元件包括用于可配置地提供一对透明存储元件的并行分布式路径。 该对可配置存储元件可以配置为不透明（即时钟）存储元件或透明可配置存储元件。 在一些实施例中，路由结构中的可配置存储元件通过包括时钟存储元件和旁路连接的并行分布式路径来执行路由和存储操作。 在一些实施例中，可配置存储元件通过一对主从锁存器执行路由和存储操作，但是没有旁路连接。 在一些实施例中，路由结构支持通过使用可配置为在不同时钟周期中执行路由和存储操作的可配置存储元件从一个时钟周期借用时钟到另一个时钟周期。 在一些实施例中，路由结构提供低功率可配置存储元件，其包括在较慢运行时钟的不同阶段操作的多个存储元件。

公开(公告)号：US09659124B2

公开(公告)日：2017-05-23

申请号：US14555436

申请日：2014-11-26

申请人： Altera Corporation

发明人： Brad Hutchings ,  Andrew Caldwell ,  Steven Teig

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5045 ,  G06F2217/84

摘要： Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.

公开(公告)号：US09606176B2

公开(公告)日：2017-03-28

申请号：US14627856

申请日：2015-02-20

申请人： Altera Corporation

发明人： Marc Miller ,  Steven Teig ,  Jason Redgrave ,  Brad Hutchings ,  Danny Thom

IPC分类号： G01R31/28 ,  G01R31/3177

CPC分类号： G01R31/3177 ,  G06F11/221 ,  G11C2029/0409

摘要： Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.

公开(公告)号：US09507900B2

公开(公告)日：2016-11-29

申请号：US14246970

申请日：2014-04-07

申请人： Altera Corporation

发明人： Andrew Caldwell ,  Herman Schmit ,  Steven Teig

IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/177

CPC分类号： G06F17/5054 ,  G06F17/505 ,  H03K19/1737 ,  H03K19/177

摘要： Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.

摘要翻译： 本发明的一些实施例提供了可配置的集成电路（“IC”）。 可配置IC包括一组多路复用器，每组具有一组输入端子，一组输出端子和一组选择端子。 该组多路复用器包括一组多路复用器，其中组中的每个多路复用器的至少一个输入端是永久反相输入端。 在可配置IC的操作期间的至少一组周期期间，使用多路复用器组中的多个多路复用器来实现特定功能。

公开(公告)号：US09436794B2

公开(公告)日：2016-09-06

申请号：US14582971

申请日：2014-12-24

申请人： Altera Corporation

发明人： Steven Teig ,  Andrew Caldwell

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5031 ,  G06F17/505 ,  G06F2217/84

摘要： A method of optimizing timing performance of an IC design expressed as a graph that includes several nodes representing IC components is provided. The method identifies several paths in the graph. Each path starts from a timed source node and ends to a timed target node. Each path includes several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to one or more clocked elements in a set of paths to satisfy timing constraints. The method identifies a path that includes a set of edge-triggered clocked elements and does not satisfy the set of timing constraints. The method replaces each edge-triggered clocked element in the identified path with a level-sensitive clocked element and optimizes the timing performance of the IC design by skewing clock signals one or more clocked element in the identified path.

摘要翻译： 提供了一种优化表示为包括表示IC组件的几个节点的图形的IC设计的定时性能的方法。 该方法识别图中的几个路径。 每个路径从定时源节点开始，并结束到定时目标节点。 每个路径包括几个时钟元素和几个计算元素。 该方法通过将时钟信号偏移到一组路径中的一个或多个时钟元件来优化IC设计的定时性能，以满足时序约束。 该方法识别包括一组边缘触发的时钟元素的路径，并且不满足时序约束的集合。 该方法用等级敏感时钟元件替代识别的路径中的每个边沿触发时钟元件，并通过在所识别的路径中偏移时钟信号一个或多个时钟元件来优化IC设计的定时性能。

公开(公告)号：US20150324508A1

公开(公告)日：2015-11-12

申请号：US14703822

申请日：2015-05-04

申请人： Altera Corporation

发明人： Eric A. Sather ,  Steven Teig

IPC分类号： G06F17/50 ,  G06F17/16

CPC分类号： G06F17/5054 ,  G06F9/00 ,  G06F15/177 ,  G06F17/16 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： A system and method of determining paths of components when placing and routing configurable circuits. The method identifies a probabilistic data flow through multiple components using a simplified connection matrix. The simplified connection matrix is used to determine a probabilistic data flow through the components without data flowing from any component to itself. The probabilistic data flow is used to determine a probabilistic data flow through the components with some of the components having data flowing from themselves back to themselves. The probabilistic data flow through each component and the number of inputs of the components are used to determine a cost for each component. The cost of a path through the circuit is determined from the costs of the individual components in the path. The costs of the components are used to determine which path of components to use.

摘要翻译： 在配置和布线可配置电路时确定组件路径的系统和方法。 该方法使用简化的连接矩阵来识别通过多个组件的概率数据流。 简化的连接矩阵用于确定通过组件的概率数据流，而没有数据从任何组件流向自身。 概率数据流用于确定通过组件的概率数据流，其中一些组件具有从自身返回到自身的数据。 通过每个组件的概率数据流和组件的输入数量用于确定每个组件的成本。 通过电路的路径的成本由路径中各个组件的成本确定。 组件的成本用于确定要使用的组件路径。

公开(公告)号：US09494967B2

公开(公告)日：2016-11-15

申请号：US14279159

申请日：2014-05-15

申请人： Altera Corporation

发明人： Brad Hutchings ,  Jason Redgrave ,  Dai Huang ,  Steven Teig

IPC分类号： H03K19/0175 ,  G06F1/04 ,  G06M3/00 ,  H03K19/177

CPC分类号： G06F1/04 ,  G06M3/00 ,  H03K19/017581 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1776 ,  H03K19/17764

摘要： Some embodiments provide an integrated circuit (“IC”). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred.

摘要翻译： 一些实施例提供集成电路（“IC”）。 IC包括可配置地基于配置数据执行用户设计操作的多个可配置电路。 IC还包括可配置触发电路，其接收指定操作事件的一组配置数据。 可配置触发电路还确定在实施IC的用户设计期间是否发生了操作事件。 此外，当确定操作触发事件已经发生时，操作触发事件输出触发信号。