公开(公告)号：US11936393B1

公开(公告)日：2024-03-19

申请号：US17805670

申请日：2022-06-06

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Moshe Raz ,  Zvika Glaubach

IPC: H03L7/00 ,  G11C11/406 ,  H03L7/099 ,  H03L7/12

CPC classification number: H03L7/12 ,  G11C11/40615 ,  G11C11/40618 ,  H03L7/0992

Abstract: Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.

公开(公告)号：US12050486B1

公开(公告)日：2024-07-30

申请号：US17805672

申请日：2022-06-06

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Moshe Raz ,  Zvika Glaubach ,  Moshe Noah

IPC: G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00

CPC classification number: G06F1/12

Abstract: Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.

公开(公告)号：US12216921B1

公开(公告)日：2025-02-04

申请号：US17710489

申请日：2022-03-31

Applicant: Amazon Technologies, Inc.

Inventor： Erez Tsidon ,  Ori Cohen ,  Barak Wasserstrom ,  Andrew Robert Sinton ,  Asaf Modelevsky ,  Moshe Raz

IPC: G06F3/06

Abstract: Technologies are disclosed for using hardware-embedded monitors to monitor pages of local memory and detect attribute violations or other unauthorized operations relating to the memory. The attribute violations may include mismatches of attributes (e.g., designating a page as writeable versus executable or vice versa) in entries in a translation buffer that point to a same physical address or other mismatches between designations of attributes for a page in physical and virtual space. Responsive to detecting a violation, an alert or other mitigation protocol, which may include an audit of activities surrounding the violation, may be performed.

公开(公告)号：US12189563B1

公开(公告)日：2025-01-07

申请号：US17937143

申请日：2022-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Moshe Raz

IPC: G06F13/40 ,  G06F13/16

Abstract: Systems and methods are provided to improve system performance when multiple transaction retry events associated with transaction requests from requester nodes to completer nodes are detected. A retry monitor can monitor the transaction retry events associated with the transaction requests to provide retry information. An intervention level generator can receive information about the transaction retry events and determine an intervention level from a plurality of intervention levels based on the retry information and a retry configuration. Each requester node can be coupled to a regulator to regulate the transactions being requested by that requester node based on the intervention level and a regulator configuration, which can allow the corresponding completer nodes to complete the outstanding transactions and reduce the occurrence of retry events.

公开(公告)号：US11860781B1

公开(公告)日：2024-01-02

申请号：US17662062

申请日：2022-05-04

Applicant: Amazon Technologies, Inc.

Inventor： Moshe Raz ,  Guy Nakibly ,  Gal Avisar

IPC: G06F12/00 ,  G06F12/0802 ,  G06F3/06

CPC classification number: G06F12/0802 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0673 ,  G06F2212/60

Abstract: A write cleaner circuit can be used to implement write-through (WT) functionality by a write-back (WB) cache memory for updating the system memory. The write cleaner circuit can intercept memory write transactions issued to the WB cache memory and generate clean requests that can enable the WB cache memory to send update requests to corresponding memory locations in the system memory around the same time as the memory write transactions are performed by the WB cache memory, and clear dirty bits in the cache lines corresponding to those memory write transactions.