公开(公告)号：US20210104948A1

公开(公告)日：2021-04-08

申请号：US17121593

申请日：2020-12-14

申请人： Ambiq Micro, Inc.

发明人： Ivan Bogue ,  Yousof Mortazavi

IPC分类号： H02M3/158 ,  H03K17/0814

摘要： A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

公开(公告)号：US12050789B2

公开(公告)日：2024-07-30

申请号：US17981149

申请日：2022-11-04

申请人： Ambiq Micro, Inc.

发明人： Daniel Martin Cermak ,  Scott McLean Hanson ,  Yousof Mortazavi ,  Ramakanth Kondagunturi

IPC分类号： G06F3/06

CPC分类号： G06F3/0625 ,  G06F3/0626 ,  G06F3/0655 ,  G06F3/0673

摘要： A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

公开(公告)号：US20230400909A1

公开(公告)日：2023-12-14

申请号：US18093907

申请日：2023-01-06

申请人： Ambiq Micro, INc.

发明人： Ivan Bogue ,  Yousof Mortazavi ,  Jesse Coulon ,  Rajeev Srivastava

IPC分类号： G06F1/3296 ,  G06F1/26

CPC分类号： G06F1/3296 ,  G06F1/263

摘要： In some embodiments, a system comprises a microcontroller system comprising a CPU, an I/O module, and a microcontroller system power input, a power supply comprising a first power supply output providing power at a first power level, and a second power supply output providing power at a second power level, and a switch comprising a signal input communicatively coupled to the I/O module and configured to receive a status signal from the I/O module, a first switch power input electrically coupled to the first power supply output, a second switch power input electrically coupled to the second power supply output, and a switch power output electrically coupled to the microcontroller system power input and configured to output power to the microcontroller system.

公开(公告)号：US20240354012A1

公开(公告)日：2024-10-24

申请号：US18760849

申请日：2024-07-01

申请人： Ambiq Micro, Inc.

发明人： Daniel Martin Cermak ,  Scott McLean Hanson ,  Yousof Mortazavi ,  Ramakanth Kondagunturi

IPC分类号： G06F3/06

CPC分类号： G06F3/0625 ,  G06F3/0626 ,  G06F3/0655 ,  G06F3/0673

摘要： A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

公开(公告)号：US12045116B2

公开(公告)日：2024-07-23

申请号：US18093907

申请日：2023-01-06

申请人： Ambiq Micro, INc.

发明人： Ivan Bogue ,  Yousof Mortazavi ,  Jesse Coulon ,  Rajeev Srivastava

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/3296

CPC分类号： G06F1/3296 ,  G06F1/263

摘要： A system comprises a microcontroller system comprising a CPU, an I/O module, and a microcontroller system power input, a power supply comprising a first power supply output providing power at a first power level, and a second power supply output providing power at a second power level, and a switch comprising a signal input communicatively coupled to the I/O module and configured to receive a status signal from the I/O module, a first switch power input electrically coupled to the first power supply output, a second switch power input electrically coupled to the second power supply output, and a switch power output electrically coupled to the microcontroller system power input and configured to output power to the microcontroller system.

公开(公告)号：US11573624B1

公开(公告)日：2023-02-07

申请号：US17835217

申请日：2022-06-08

申请人： Ambiq Micro, Inc.

发明人： Ivan Bogue ,  Yousof Mortazavi ,  Jesse Coulon ,  Rajeev Srivastava

IPC分类号： G06F1/00 ,  G06F1/3296 ,  G06F1/26

摘要： In some embodiments, a system comprises a microcontroller system comprising a CPU, an I/O module, and a microcontroller system power input, a power supply comprising a first power supply output providing power at a first power level, and a second power supply output providing power at a second power level, and a switch comprising a signal input communicatively coupled to the I/O module and configured to receive a status signal from the I/O module, a first switch power input electrically coupled to the first power supply output, a second switch power input electrically coupled to the second power supply output, and a switch power output electrically coupled to the microcontroller system power input and configured to output power to the microcontroller system.

公开(公告)号：US20230376222A1

公开(公告)日：2023-11-23

申请号：US17981149

申请日：2022-11-04

申请人： Ambiq Micro, Inc.

发明人： Daniel Martin Cermak ,  Scott McLean Hanson ,  Yousof Mortazavi ,  Ramakanth Kondagunturi

IPC分类号： G06F3/06

CPC分类号： G06F3/0625 ,  G06F3/0626 ,  G06F3/0655 ,  G06F3/0673

摘要： A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

公开(公告)号：US11520499B1

公开(公告)日：2022-12-06

申请号：US17747410

申请日：2022-05-18

申请人： Ambiq Micro, Inc.

发明人： Daniel Martin Cermak ,  Scott McLean Hanson ,  Yousof Mortazavi ,  Ramakanth Kondagunturi

IPC分类号： G06F3/06

摘要： A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

公开(公告)号：US20200321875A1

公开(公告)日：2020-10-08

申请号：US16375391

申请日：2019-04-04

申请人： Ambiq Micro, Inc.

发明人： Ivan Bogue ,  Yousof Mortazavi

IPC分类号： H02M3/158 ,  H03K17/0814

摘要： A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

公开(公告)号：US20200321866A1

公开(公告)日：2020-10-08

申请号：US16375526

申请日：2019-04-04

申请人： Ambiq Micro, Inc.

发明人： Ivan Bogue ,  Yousof Mortazavi

IPC分类号： H02M3/158 ,  H02M3/157

摘要： A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.