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    Stacked gate memory cell with erase to gate, array, and method of manufacturing
    4.
    发明申请
    Stacked gate memory cell with erase to gate, array, and method of manufacturing 有权
    具有擦除到栅极，阵列和制造方法的堆叠栅极存储单元

    公开(公告)号：US20060091449A1

    公开(公告)日：2006-05-04

    申请号：US11303567

    申请日：2005-12-15

    申请人： Bomy Chen ,  Hieu Tran ,  Dana Lee ,  Jack Frayer

    发明人： Bomy Chen ,  Hieu Tran ,  Dana Lee ,  Jack Frayer

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/7885

    摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.

    摘要翻译： 堆叠式非易失性存储器浮栅器件具有控制栅极。 通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。 擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。 最后，为了增加密度，可以在沟槽中制造每个单元。

    Word line voltage boosting circuit and a memory array incorporating same
    5.
    发明申请
    Word line voltage boosting circuit and a memory array incorporating same 有权

    公开(公告)号：US20070076489A1

    公开(公告)日：2007-04-05

    申请号：US11241582

    申请日：2005-09-30

    申请人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Tran ,  Jack Frayer ,  Bomy Chen

    发明人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Tran ,  Jack Frayer ,  Bomy Chen

    IPC分类号： G11C11/34

    CPC分类号： G11C8/08 ,  G11C16/08

    摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

    Isolation-less, contact-less array of nonvolatile memory cells each having a floating gate for storage of charges, and methods of manufacturing, and operating therefor
    6.
    发明申请
    Isolation-less, contact-less array of nonvolatile memory cells each having a floating gate for storage of charges, and methods of manufacturing, and operating therefor 有权
    非易失性存储单元的无隔离阵列，每个非易失性存储单元均具有用于存储电荷的浮动栅极，以及制造方法和操作方法

    公开(公告)号：US20050224861A1

    公开(公告)日：2005-10-13

    申请号：US10822944

    申请日：2004-04-12

    申请人： Dana Lee ,  Hieu Tran ,  Jack Frayer

    发明人： Dana Lee ,  Hieu Tran ,  Jack Frayer

    IPC分类号： H01L21/8247 ,  G11C16/04 ,  G11C16/14 ,  H01L21/28 ,  H01L21/336 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/7881 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0491 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7887

    摘要： An isolation-less, contact-less nonvolatile memory array has a plurality of memory cells each with a floating gate for the storage of charges thereon, arranged in a plurality of rows and columns. Each memory cell can be of a number of different types. All the bit lines and source lines of the various embodiments are buried and are contact-less. In a first embodiment, each cell can be represented by a stacked gate floating gate transistor coupled to a separate assist transistor. The entire array can be planar; or in a preferred embodiment each of the floating gate transistors is in a trench; or each of the assist transistors is in a trench. In a second embodiment, each cell can be represented by a stacked gate floating gate transistor with the transistor in a trench. In a third embodiment, each cell can be represented by two stacked gate floating gate transistors coupled to a separate assist transistor, positioned between the two stacked gate floating gate transistors. The entire array can be planar; or in a preferred embodiment each of the floating gate transistors is in a trench; or each of the assist transistors is in a trench. Novel methods to manufacture the arrays and methods to program, erase, and read each of these embodiments of the memory cells is disclosed.

    摘要翻译： 无隔离的非接触式非易失性存储器阵列具有多个存储单元，每个存储单元具有用于在其上存储电荷的浮动栅极，其布置成多个行和列。 每个存储单元可以是多种不同的类型。 各种实施例的所有位线和源极线被掩埋并且是无接触的。 在第一实施例中，每个单元可以由耦合到单独的辅助晶体管的堆叠栅极浮栅晶体管表示。 整个阵列可以是平面的; 或者在优选实施例中，每个浮栅晶体管处于沟槽中; 或者每个辅助晶体管处于沟槽中。 在第二实施例中，每个单元可以由晶体管在沟槽中的层叠栅极浮栅晶体管表示。 在第三实施例中，每个单元可以由耦合到位于两个堆叠的栅极浮置栅极晶体管之间的单独的辅助晶体管的两个堆叠的栅极浮栅晶体管表示。 整个阵列可以是平面的; 或者在优选实施例中，每个浮栅晶体管处于沟槽中; 或者每个辅助晶体管处于沟槽中。 公开了制造阵列的新方法和编程，擦除和读取存储器单元的这些实施例的每一个的方法。

    Bi-directional read/program non-volatile floating gate memory cell and array thereof, and method of formation
    7.
    发明授权
    Bi-directional read/program non-volatile floating gate memory cell and array thereof, and method of formation 有权
    双向读/写非易失性浮栅存储单元及其阵列及其形成方法

    公开(公告)号：US07151021B2

    公开(公告)日：2006-12-19

    申请号：US11111244

    申请日：2005-04-20

    申请人： Bomy Chen ,  Jack Frayer ,  Dana Lee

    发明人： Bomy Chen ,  Jack Frayer ,  Dana Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/11521 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7887

    摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate.

    摘要翻译： 双向读/写非易失性存储单元和阵列能够实现高密度。 每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。 浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。 控制栅极连接到每个源极/漏极区域，并且还电容耦合到浮动栅极。 通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。 双向读取允许将单元编程为存储位，每个浮动栅极中有一位。

    Bi-directional read/program non-volatile floating gate memory cell and array thereof, and method of formation
    8.
    发明申请
    Bi-directional read/program non-volatile floating gate memory cell and array thereof, and method of formation 有权
    双向读/写非易失性浮栅存储单元及其阵列及其形成方法

    公开(公告)号：US20050237807A1

    公开(公告)日：2005-10-27

    申请号：US11111244

    申请日：2005-04-20

    申请人： Bomy Chen ,  Jack Frayer ,  Dana Lee

    发明人： Bomy Chen ,  Jack Frayer ,  Dana Lee

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7887

    摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate.

    摘要翻译： 双向读/写非易失性存储单元和阵列能够实现高密度。 每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。 浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。 控制栅极连接到每个源极/漏极区域，并且还电容耦合到浮动栅极。 通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。 双向读取允许将单元编程为存储位，每个浮动栅极中有一位。

    High speed and high precision sensing for digital multilevel non-volatile memory system
    10.
    发明申请
    High speed and high precision sensing for digital multilevel non-volatile memory system 有权

    公开(公告)号：US20060072363A1

    公开(公告)日：2006-04-06

    申请号：US11283195

    申请日：2005-11-18

    申请人： Hieu Tran ,  Jack Frayer ,  William Saiki ,  Michael Briner

    发明人： Hieu Tran ,  Jack Frayer ,  William Saiki ,  Michael Briner

    IPC分类号： G11C7/02

    CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C16/28

    摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.