公开(公告)号：US10374583B1

公开(公告)日：2019-08-06

申请号：US15943341

申请日：2018-04-02

Applicant: Analog Devices, Inc.

Inventor： Piotr Olejarz ,  Daniel Saari ,  Ara Arakelian

IPC: H03K3/00 ,  H03K3/0233 ,  H03K3/037 ,  H03K5/08 ,  H04L7/00 ,  G06F13/38 ,  G06F13/42 ,  G06F13/24 ,  H04J3/06 ,  G06F13/40 ,  G06F16/60

Abstract: A method is described and in one embodiment includes detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode; placing the circuit in a second hysteresis mode subsequent to the detecting; and returning the receiver to the first hysteresis mode subsequent to completion of receipt of the data packet to await receipt of a next data packet. In certain embodiments, the first hysteresis mode is a high hysteresis mode and the second hysteresis mode is a standard hysteresis mode. In some embodiments, a level of each of the first and second hysteresis modes is dynamically tunable.

公开(公告)号：US20230402448A1

公开(公告)日：2023-12-14

申请号：US17806903

申请日：2022-06-14

Applicant: Analog Devices, Inc.

Inventor： Sirui Luo ,  Srivatsan Parthasarathy ,  Piotr Olejarz ,  Daniel Boyko ,  Ara Arakelian ,  Stuart Patterson

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0262 ,  H02H9/046

Abstract: Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.

公开(公告)号：US11942473B2

公开(公告)日：2024-03-26

申请号：US17806903

申请日：2022-06-14

Applicant: Analog Devices, Inc.

Inventor： Sirui Luo ,  Srivatsan Parthasarathy ,  Piotr Olejarz ,  Daniel Boyko ,  Ara Arakelian ,  Stuart Patterson

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0262 ,  H02H9/046

Abstract: Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.

公开(公告)号：US09077512B2

公开(公告)日：2015-07-07

申请号：US14030824

申请日：2013-09-18

Applicant: Analog Devices, Inc.

Inventor： Piotr Olejarz ,  Ara Arakelian ,  Lewis Malaver

IPC: H04L7/033 ,  H03L7/08

CPC classification number: H04L7/0332 ,  H03L7/0805 ,  H03L7/095 ,  H04L7/033

Abstract: A clock alignment detector described herein can detect alignment between clock signals within a defined margin of error, such as a defined margin of phase error. The margin of phase error can be varied to achieve various degrees of lock detection precision. Clock alignment detector can detect alignment between rising edges of the clock signals, falling edges of the clock signals, or both the rising and falling edges of the clock signals. The clock alignment detector can be implemented as a lock detector for a phase-locked loop that is configured to detect and maintain a phase relationship between a reference clock signal and a feedback clock signal, where the clock alignment detector detects alignment between the reference clock signal and the feedback clock signal.

Abstract translation: 本文描述的时钟对准检测器可以检测定义的误差范围内的时钟信号之间的对准，例如定义的相位误差余量。 可以改变相位误差的幅度，以达到各种程度的锁定检测精度。 时钟对准检测器可以检测时钟信号的上升沿，时钟信号的下降沿或时钟信号的上升沿和下降沿之间的对准。 时钟对准检测器可以被实现为用于锁相环的锁定检测器，其被配置为检测和维持参考时钟信号和反馈时钟信号之间的相位关系，其中时钟对准检测器检测参考时钟信号 和反馈时钟信号。

公开(公告)号：US20150078501A1

公开(公告)日：2015-03-19

申请号：US14030824

申请日：2013-09-18

Applicant: ANALOG DEVICES, INC.

Inventor： Piotr Olejarz ,  Ara Arakelian ,  Lewis Malaver

IPC: H04L7/033

CPC classification number: H04L7/0332 ,  H03L7/0805 ,  H03L7/095 ,  H04L7/033

Abstract: A clock alignment detector described herein can detect alignment between clock signals within a defined margin of error, such as a defined margin of phase error. The margin of phase error can be varied to achieve various degrees of lock detection precision. Clock alignment detector can detect alignment between rising edges of the clock signals, falling edges of the clock signals, or both the rising and falling edges of the clock signals. The clock alignment detector can be implemented as a lock detector for a phase-locked loop that is configured to detect and maintain a phase relationship between a reference clock signal and a feedback clock signal, where the clock alignment detector detects alignment between the reference clock signal and the feedback clock signal.

Abstract translation: 本文描述的时钟对准检测器可以检测定义的误差范围内的时钟信号之间的对准，例如定义的相位误差余量。 可以改变相位误差的幅度，以达到各种程度的锁定检测精度。 时钟对准检测器可以检测时钟信号的上升沿，时钟信号的下降沿或时钟信号的上升沿和下降沿之间的对准。 时钟对准检测器可以被实现为用于锁相环的锁定检测器，其被配置为检测和维持参考时钟信号和反馈时钟信号之间的相位关系，其中时钟对准检测器检测参考时钟信号 和反馈时钟信号。