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公开(公告)号：US20230402448A1
公开(公告)日：2023-12-14
申请号：US17806903
申请日：2022-06-14
Applicant: Analog Devices, Inc.
Inventor： Sirui Luo , Srivatsan Parthasarathy , Piotr Olejarz , Daniel Boyko , Ara Arakelian , Stuart Patterson
CPC classification number: H01L27/0262 , H02H9/046
Abstract: Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.
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公开(公告)号：US10374583B1
公开(公告)日：2019-08-06
申请号：US15943341
申请日：2018-04-02
Applicant: Analog Devices, Inc.
Inventor： Piotr Olejarz , Daniel Saari , Ara Arakelian
IPC: H03K3/00 , H03K3/0233 , H03K3/037 , H03K5/08 , H04L7/00 , G06F13/38 , G06F13/42 , G06F13/24 , H04J3/06 , G06F13/40 , G06F16/60
Abstract: A method is described and in one embodiment includes detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode; placing the circuit in a second hysteresis mode subsequent to the detecting; and returning the receiver to the first hysteresis mode subsequent to completion of receipt of the data packet to await receipt of a next data packet. In certain embodiments, the first hysteresis mode is a high hysteresis mode and the second hysteresis mode is a standard hysteresis mode. In some embodiments, a level of each of the first and second hysteresis modes is dynamically tunable.
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Patent Agency Ranking
公开(公告)号：US20160091909A1
公开(公告)日：2016-03-31
申请号：US14563453
申请日：2014-12-08
Applicant: Analog Devices, Inc.
Inventor： Piotr Olejarz
Abstract: A voltage regulator is provided comprising: a pass transistor that includes a first node coupled to receive an input voltage and a second node coupled to provide a regulated voltage and a control node; an amplifier circuit coupled to produce a control voltage on a control line that is coupled to control a voltage at the control node of the pass transistor, based at least in part upon a reference voltage and the regulated voltage; a switch configured to transition between a first switch state in which the switch couples the control line to a turn-off voltage having a value to turn off the pass transistor and a second switch state in which the switch decouples the control line from the turn-off voltage; and a switch control circuit configured to maintain the switch in the first switch state during a first time interval while the input voltage ramps up and to transition the switch to the second switch state after the first time interval.
Abstract translation: 提供一种电压调节器，包括：通过晶体管，其包括耦合以接收输入电压的第一节点和耦合以提供调节电压的第二节点和控制节点; 放大器电路，其被耦合以至少部分地基于参考电压和所述调节电压在控制线上产生控制电压，所述控制线被耦合以控制所述传输晶体管的控制节点处的电压; 开关，被配置为在开关将控制线耦合到具有关闭所述通过晶体管的值的关断电压的第一开关状态和所述开关将所述控制线与所述转向开关断开的第二开关状态之间转换， 关断电压; 以及开关控制电路，被配置为在所述输入电压上升期间的第一时间间隔期间将所述开关保持在所述第一开关状态，并且在所述第一时间间隔之后将所述开关转换到所述第二开关状态。
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公开(公告)号：US11942473B2
公开(公告)日：2024-03-26
申请号：US17806903
申请日：2022-06-14
Applicant: Analog Devices, Inc.
Inventor： Sirui Luo , Srivatsan Parthasarathy , Piotr Olejarz , Daniel Boyko , Ara Arakelian , Stuart Patterson
CPC classification number: H01L27/0262 , H02H9/046
Abstract: Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.
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公开(公告)号：US10001794B2
公开(公告)日：2018-06-19
申请号：US14563453
申请日：2014-12-08
Applicant: Analog Devices, Inc.
Inventor： Piotr Olejarz
Abstract: A voltage regulator is provided comprising: a pass transistor that includes a first node coupled to receive an input voltage and a second node coupled to provide a regulated voltage and a control node; an amplifier circuit coupled to produce a control voltage on a control line that is coupled to control a voltage at the control node of the pass transistor, based at least in part upon a reference voltage and the regulated voltage; a switch configured to transition between a first switch state in which the switch couples the control line to a turn-off voltage having a value to turn off the pass transistor and a second switch state in which the switch decouples the control line from the turn-off voltage; and a switch control circuit configured to maintain the switch in the first switch state during a first time interval while the input voltage ramps up and to transition the switch to the second switch state after the first time interval.
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公开(公告)号：US09077512B2
公开(公告)日：2015-07-07
申请号：US14030824
申请日：2013-09-18
Applicant: Analog Devices, Inc.
Inventor： Piotr Olejarz , Ara Arakelian , Lewis Malaver
CPC classification number: H04L7/0332 , H03L7/0805 , H03L7/095 , H04L7/033
Abstract: A clock alignment detector described herein can detect alignment between clock signals within a defined margin of error, such as a defined margin of phase error. The margin of phase error can be varied to achieve various degrees of lock detection precision. Clock alignment detector can detect alignment between rising edges of the clock signals, falling edges of the clock signals, or both the rising and falling edges of the clock signals. The clock alignment detector can be implemented as a lock detector for a phase-locked loop that is configured to detect and maintain a phase relationship between a reference clock signal and a feedback clock signal, where the clock alignment detector detects alignment between the reference clock signal and the feedback clock signal.
Abstract translation: 本文描述的时钟对准检测器可以检测定义的误差范围内的时钟信号之间的对准，例如定义的相位误差余量。 可以改变相位误差的幅度，以达到各种程度的锁定检测精度。 时钟对准检测器可以检测时钟信号的上升沿，时钟信号的下降沿或时钟信号的上升沿和下降沿之间的对准。 时钟对准检测器可以被实现为用于锁相环的锁定检测器，其被配置为检测和维持参考时钟信号和反馈时钟信号之间的相位关系，其中时钟对准检测器检测参考时钟信号 和反馈时钟信号。
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公开(公告)号：US20150078501A1
公开(公告)日：2015-03-19
申请号：US14030824
申请日：2013-09-18
Applicant: ANALOG DEVICES, INC.
Inventor： Piotr Olejarz , Ara Arakelian , Lewis Malaver
IPC: H04L7/033
CPC classification number: H04L7/0332 , H03L7/0805 , H03L7/095 , H04L7/033
Abstract: A clock alignment detector described herein can detect alignment between clock signals within a defined margin of error, such as a defined margin of phase error. The margin of phase error can be varied to achieve various degrees of lock detection precision. Clock alignment detector can detect alignment between rising edges of the clock signals, falling edges of the clock signals, or both the rising and falling edges of the clock signals. The clock alignment detector can be implemented as a lock detector for a phase-locked loop that is configured to detect and maintain a phase relationship between a reference clock signal and a feedback clock signal, where the clock alignment detector detects alignment between the reference clock signal and the feedback clock signal.
Abstract translation: 本文描述的时钟对准检测器可以检测定义的误差范围内的时钟信号之间的对准，例如定义的相位误差余量。 可以改变相位误差的幅度，以达到各种程度的锁定检测精度。 时钟对准检测器可以检测时钟信号的上升沿，时钟信号的下降沿或时钟信号的上升沿和下降沿之间的对准。 时钟对准检测器可以被实现为用于锁相环的锁定检测器，其被配置为检测和维持参考时钟信号和反馈时钟信号之间的相位关系，其中时钟对准检测器检测参考时钟信号 和反馈时钟信号。
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