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    Analog ultrasound beamformer
    3.
    发明授权
    Analog ultrasound beamformer 有权

    公开(公告)号：US10656254B2

    公开(公告)日：2020-05-19

    申请号：US15352760

    申请日：2016-11-16

    Applicant: ANALOG DEVICES, INC.

    Inventor： Eric G. Nestler

    IPC: G01S7/52 ,  G10K11/34 ,  G01S15/89 ,  A61B8/08 ,  A61B8/06 ,  A61B8/00

    Abstract: A sampled analog beamformer for ultrasound beamforming includes an array of transducers for transmitting analog signals and receiving reflected analog signals, and a sampled analog filter for filtering the received reflected analog. The sampled analog filter includes a delay line for adding a delay to each of the received reflected analog signals. Using a sampled analog filter in an ultrasound beamforming system reduces the power usage of the system and decreases the number of components in the system.

    High precision sampled analog circuits
    4.
    发明授权
    High precision sampled analog circuits 有权

    公开(公告)号：US09847789B1

    公开(公告)日：2017-12-19

    申请号：US15451776

    申请日：2017-03-07

    Applicant: Analog Devices, Inc.

    Inventor： Mikael Mortensen ,  Eric G. Nestler

    IPC: H03M1/12 ,  H03M1/00 ,  H03M1/80

    CPC classification number: H03M1/0626 ,  H03H15/02 ,  H03M1/00 ,  H03M1/12 ,  H03M1/804

    Abstract: A sampled analog circuit is divided into at least two segments, each segment receiving sampled analog data and a respective subset of bits of a filter coefficient. The at least two segments can have digital-to-capacitance circuits with substantially identical ranges of capacitance values. One or more outputs from the segments can be scaled to reflect a position of the subset of bits in the bits of the filter coefficient, and thereafter added in the analog domain to produce a filtered output signal that may then be digitized. Alternatively, the outputs from the segments may be digitized before being scaled and/or added in the digital domain.

    Convolutional neural network
    5.
    发明授权
    Convolutional neural network 有权

    公开(公告)号：US11475269B2

    公开(公告)日：2022-10-18

    申请号：US15379114

    申请日：2016-12-14

    Applicant: Analog Devices, Inc.

    Inventor： Eric G. Nestler ,  Mitra M. Osqui ,  Jeffrey G. Bernstein

    IPC: G06N3/04 ,  G06N3/063 ,  H03M1/80

    Abstract: Systems and methods of implementing a more efficient and less resource-intensive CNN are disclosed herein. In particular, applications of CNN in the analog domain using Sampled Analog Technology (SAT) methods are disclosed. Using a CNN design with SAT results in lower power usage and faster operation as compared to a CNN design with digital logic and memory. The lower power usage of a CNN design with SAT can allow for sensor devices that also detect features at very low power for isolated operation.

    Techniques for power efficient oversampling successive approximation register
    6.
    发明授权
    Techniques for power efficient oversampling successive approximation register 有权

    公开(公告)号：US10340932B2

    公开(公告)日：2019-07-02

    申请号：US15583183

    申请日：2017-05-01

    Applicant: Analog Devices, Inc.

    Inventor： Abhishek Bandyopadhyay ,  Dan Boyko ,  Eric G. Nestler

    IPC: H03M1/12 ,  H03M1/08 ,  H03M1/00

    Abstract: Systems and methods are disclosed for a noise-shaping successive approximation register (SAR) analog-to-digital-converter (ADC) using Sampled Analog Technology (SAT) filter techniques for filter construction. A SAR ADC includes an SAR for receiving an analog input signal and outputting a digital decision, a digital-to-analog converter and logic circuitry for converting the digital decision of the SAR to a present analog residue for a present conversion cycle, a filter for processing a previous analog residue from a previous conversion cycle, and for feeding a processed previous analog residue back to the SAR, a summer for summing the processed previous analog residue from the filter and the present analog residue, and generating a summer output, and a comparator for comparing the summer output and a first reference signal and generating a comparator output. The filter includes a capacitor array for filtering the previous analog residue to generate the processed previous analog residue.

    Synchronous charge sharing filter
    7.
    发明授权
    Synchronous charge sharing filter 有权
    同步电荷共享滤波器

    公开(公告)号：US09559662B2

    公开(公告)日：2017-01-31

    申请号：US14879975

    申请日：2015-10-09

    Applicant: ANALOG DEVICES, INC.

    Inventor： Eric G. Nestler

    IPC: H03K5/00 ,  H03H11/04 ,  H03H15/00

    CPC classification number: H03H11/0405 ,  H03H15/00

    Abstract: A signal processing device has a first discrete time analog signal processing section, which has an input, an output, a plurality of charge storage elements, and plurality of switch elements coupling the charge storage elements. The device has a controller coupled to the first signal processing section configured to couple different subsets of the charge elements of the first signal processing section in successive operating phases to apply a signal processing function to an analog signal presented at the input of the first signal processing section and provide a result of the applying of the signal processing function as an analog signal to the output of first signal processing section. The signal processing function of the first signal processing section comprises a combination of a filtering function operating at a first sampling rate and one or more modulation functions operating at corresponding modulation rates lower than the first sampling rate.

    Abstract translation: 信号处理装置具有第一离散时间模拟信号处理部分，其具有输入，输出，多个电荷存储元件以及耦合电荷存储元件的多个开关元件。 该设备具有耦合到第一信号处理部分的控制器，其被配置为在连续的操作阶段中耦合第一信号处理部分的电荷元件的不同子集，以将信号处理功能应用于在第一信号处理的输入处呈现的模拟信号 并提供将信号处理功能作为模拟信号施加到第一信号处理部分的输出的结果。 第一信号处理部分的信号处理功能包括以第一采样率工作的滤波功能和以低于第一采样率的相应调制速率工作的一个或多个调制功能的组合。

    Sampled analog loop filter for phase locked loops
    8.
    发明授权
    Sampled analog loop filter for phase locked loops 有权
    用于锁相环的采样模拟环路滤波器

    公开(公告)号：US09537492B2

    公开(公告)日：2017-01-03

    申请号：US14745017

    申请日：2015-06-19

    Applicant: ANALOG DEVICES, INC.

    Inventor： Alexander A. Alexeyev ,  Eric G. Nestler

    IPC: H03L7/06 ,  H03L7/085

    CPC classification number: H03L7/085

    Abstract: An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter.

    Abstract translation: 集成电路实现了锁相环（PLL）的至少一部分。 集成电路包括用于PLL的采样模拟环路滤波器。 环路滤波器包括用于接收表示参考时钟信号和第一时钟信号之间的相位差的信号的第一输入端，用于提供用于控制振荡器频率的频率控制信号的第一输出端，​​用于接收振荡器的时钟输入 环路定时时钟信号，用于控制环路滤波器的操作定时;以及数字控制输入，用于根据多个控制值配置环路滤波器的响应。 在一些示例中，环路滤波器包括通过可控开关耦合的电荷存储元件和用于在电荷存储元件之间传送电荷的控制电路，以产生环路滤波器的配置响应。

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