中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.014 seconds)

    Enhancing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters
    1.
    发明授权
    Enhancing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters 有权

    公开(公告)号：US12052037B2

    公开(公告)日：2024-07-30

    申请号：US17702515

    申请日：2022-03-23

    Applicant: Analog Devices, Inc.

    Inventor： Akira Shikata ,  Abhishek Bandyopadhyay

    IPC: H03M3/00

    CPC classification number: H03M3/322 ,  H03M3/426

    Abstract: Systems and methods are provided for increasing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters. In some examples, systems and methods are provided for reducing total capacitance in an embedded excess loop delay compensation digital-to-analog converter (DAC) in a quantizer for a continuous time delta-sigma ADC. In other examples, the excess loop delay compensation DAC can be a current domain DAC, a charge domain DAC, or a voltage domain DAC. Additionally, methods are provided for digitally controlling the gain of an excess loop delay DAC. Furthermore, methods are provided to calibrate a gain mismatch between a main successive approximation register DAC and an excess loop delay DAC. The systems and methods provided herein improve performance of continuous time delta-sigma ADCs. Continuous time delta-sigma ADCs are high precision and power efficient ADCs, often used in audio playback devices and medical devices.

    Method to compensate for metastability of asynchronous SAR within delta sigma modulator loop
    3.
    发明授权
    Method to compensate for metastability of asynchronous SAR within delta sigma modulator loop 有权

    公开(公告)号：US11539373B2

    公开(公告)日：2022-12-27

    申请号：US17339369

    申请日：2021-06-04

    Applicant: Analog Devices, Inc.

    Inventor： Abhishek Bandyopadhyay

    IPC: H03M1/34 ,  H03M1/46 ,  H03M1/08 ,  H03M1/12 ,  H03M3/00

    Abstract: Herein disclosed are some examples of metastability detectors and compensator circuitry for successive-approximation-register (SAR) analog-to-digital converters (ADCs) within delta sigma modulator (DSM) loops. A metastability detector may detect metastability at an output of a SAR ADC and compensator circuitry may implement a compensation scheme to compensate for the metastability. The identification of the metastability and/or compensation for the metastability can avoid detrimental effects and/or errors to the DSM loops that may be caused by the metastability of the SAR ADCS.

    Apparatus and methods for equalization
    5.
    发明授权
    Apparatus and methods for equalization 有权
    用于均衡的装置和方法

    公开(公告)号：US09319004B2

    公开(公告)日：2016-04-19

    申请号：US13684904

    申请日：2012-11-26

    Applicant: ANALOG DEVICES, INC.

    Inventor： Abhishek Bandyopadhyay ,  David Paul Foley

    IPC: H03F1/34 ,  H03F3/45

    CPC classification number: H03F1/34 ,  H03F3/45475 ,  H03F2203/45134 ,  H03F2203/45138 ,  H03F2203/45522 ,  H03F2203/45526

    Abstract: Apparatus and methods for equalization are provided. In certain implementations, an equalizer includes first and second feedback resistors, first and second equalization resistors, an equalization capacitor, and an amplification circuit that includes first to fourth input terminals and first and second output terminals. The amplification circuit can receive a differential input voltage signal between the first and third input terminals, and the first and second equalization resistors and the equalization capacitor are electrically connected in series between the second and fourth input terminals with the equalization capacitor between the first and second equalization resistors. Additionally, the first feedback resistor is electrically connected between the first output terminal and the second input terminal, and the second feedback resistor is electrically connected between the second output terminal and the fourth input terminal.

    Abstract translation: 提供了用于均衡的装置和方法。 在某些实现中，均衡器包括第一和第二反馈电阻器，第一和第二均衡电阻器，均衡电容器和包括第一至第四输入端子和第一和第二输出端子的放大电路。 放大电路可以在第一和第三输入端子之间接收差分输入电压信号，并且第一和第二均衡电阻器和均衡电容器串联地电连接在第二和第四输入端子之间，均衡电容器在第一和第二输入端子之间 均衡电阻。 此外，第一反馈电阻器电连接在第一输出端子和第二输入端子之间，第二反馈电阻器电连接在第二输出端子和第四输入端子之间。

    Multi quantizer loops for delta-sigma converters
    8.
    发明授权
    Multi quantizer loops for delta-sigma converters 有权

    公开(公告)号：US11621722B2

    公开(公告)日：2023-04-04

    申请号：US17459020

    申请日：2021-08-27

    Applicant: Analog Devices, Inc.

    Inventor： Abhishek Bandyopadhyay ,  Akira Shikata

    IPC: H03M3/00

    Abstract: The number of bits in the quantizer can be decoupled from the number of bits in the feedback digital-to-analog converter (DAC) A delta-sigma analog-to-digital converter circuit can include a first quantizer to generate an output having a first number of bits and a second quantizer coupled to an output of the first quantizer, where the second quantizer can receive the output of the first quantizer and generate an output having a second number of bits. The feedback DAC can be coupled to the second quantizer to receive a representation of the output of the second quantizer, where the output of the feedback digital-to-analog converter circuit has the second number of bits. These techniques can reduce the area of the feedback DAC, e.g., 4 or 5 bits, and the techniques can achieve a higher maximum stable amplitude (MSA) because it is effectively a second order loop.

    TECHNIQUES TO REDUCE QUANTIZATION NOISE IN DELTA SIGMA CONVERTERS
    10.
    发明申请
    TECHNIQUES TO REDUCE QUANTIZATION NOISE IN DELTA SIGMA CONVERTERS 有权

    公开(公告)号：US20230060505A1

    公开(公告)日：2023-03-02

    申请号：US17459071

    申请日：2021-08-27

    Applicant: Analog Devices, Inc.

    Inventor： Abhishek Bandyopadhyay ,  Akira Shikata

    IPC: H03M3/00 ,  H03M1/08 ,  H03M1/68 ,  H03M1/46

    Abstract: This disclosure is directed to, among other things, techniques to decouple the number of bits in a quantizer from the number of bits in the feedback digital-to-analog converter (DAC). A delta-sigma analog-to-digital converter circuit can include a first quantizer to generate an output having a first number of bits and then emulate a second quantizer, such as by using a bit truncation technique, to generate an output having a second number of bits. The feedback DAC can be coupled to receive the second number of bits, where the output of the feedback digital-to-analog converter circuit has the second number of bits. These techniques can reduce the area of the feedback DAC, e.g., 4 or 5 bits, and the techniques can achieve a higher maximum stable amplitude (MSA) because it is effectively a second order loop.

Patent Agency Ranking