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公开(公告)号：US12119833B2
公开(公告)日：2024-10-15
申请号：US17877375
申请日：2022-07-29
Applicant: Analog Devices, Inc.
Inventor： Khiem Quang Nguyen
CPC classification number: H03M1/0604 , H03M1/0665 , H03M1/66
Abstract: Embodiments of the disclosure provide improved mismatch shaping for a digital to analog converter, the method including splitting an original input of a circuit into a plurality of time interleaved data streams; element rotation selection (ERS) logic to process the plurality of time interleaved data streams; and directing one of the plurality of time interleaved data streams to the ERS logic according to a decision of a data-weighted sigma-delta (SD) modulator. In other example implementations, the method can further include multiplexing one of the plurality of time interleaved data streams to be provided to a barrel shifter. In yet other examples, the method can include monitoring a difference between the plurality of time interleaved data streams as a basis for the directing such that a data sample rate for the digital to analog converter is reduced over a time interval.
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公开(公告)号：US10819365B1
公开(公告)日：2020-10-27
申请号：US16783442
申请日：2020-02-06
Applicant: Analog Devices, Inc.
Inventor： Khiem Quang Nguyen , Long Pham
Abstract: Improved switching techniques for controlling three-level current steering DAC cells are disclosed. The techniques include decoupling two current sources, implemented as field-effect transistors (FETs), of a DAC cell both from their respective bias sources and from a load for converting a zero digital input, where the decoupling is performed in a certain order. The techniques also include coupling the current sources to their respective bias sources and to the load for converting a non-zero digital input, where the coupling is also performed in a certain order. The certain order of decoupling and coupling the bias sources and the load to the current sources of a DAC cell are based on the phenomenon of current memory in FETs. Utilizing current memory when operating a DAC cell may allow reducing power consumption while preserving the high performance properties of a three-level current steering DAC.
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3.发明授权公开(公告)号：US09484947B1
公开(公告)日：2016-11-01
申请号：US14869154
申请日：2015-09-29
Applicant: ANALOG DEVICES, INC.
Inventor： Khiem Quang Nguyen
CPC classification number: H03M1/70 , H03M1/00 , H03M1/002 , H03M1/066 , H03M1/747 , H03M3/338 , H03M3/50
Abstract: Embodiments of the disclosure provide improved mechanisms for applying DEM techniques to a DAC comprising a plurality of cells. Disclosed mechanisms include keeping track of the amplitude of input digital signal over a certain time period to determine a range of amplitudes of a portion of the input signal, and, when converting the digital values of that portion to analog values and applying a particular DEM technique, limiting the number of DAC cells on which a DEM technique is applied only to a number that is necessary for generating the analog output corresponding to the tracked portion, which number is determined based on the tracked amplitudes and could be smaller than the total number of DAC cells. In this manner, mismatch error may be reduced for smaller input signal amplitudes. Whenever possible, unused DAC cells may be put into a power saving mode, providing the advantage of reduced power consumption.
Abstract translation: 本公开的实施例提供了用于将DEM技术应用于包括多个单元的DAC的改进机制。 公开的机制包括在一定时间段内跟踪输入数字信号的幅度以确定输入信号的一部分的幅度范围，并且当将该部分的数字值转换为模拟值并应用特定的DEM技术 限制将DEM技术应用于其上的DAC单元的数量仅限于产生与被跟踪部分相对应的模拟输出所需的数量，该数目是基于跟踪幅度确定的，并且可以小于 DAC单元。 以这种方式，对于较小的输入信号幅度，可能会降低失配误差。 只要有可能，未使用的DAC单元可以进入省电模式，提供降低功耗的优点。
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公开(公告)号：US11579165B2
公开(公告)日：2023-02-14
申请号：US16751182
申请日：2020-01-23
Applicant: Analog Devices, Inc.
Inventor： Khiem Quang Nguyen , Adam R. Spirer
Abstract: Sensor apparatus and methods for operating the same for measuring acceleration are disclosed. In some embodiments, circuitry inside a sensor digitizes a measured acceleration signal from an accelerometer into a digitized acceleration signal, which is processed by a digital equalization filter within the sensor to provide an equalized acceleration signal. The equalized acceleration signal may have a frequency response that is substantially flat over a frequency range that extends beyond the resonant frequency of a MEMs sensor within the accelerometer of the sensor.
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公开(公告)号：US09748929B1
公开(公告)日：2017-08-29
申请号：US15332732
申请日：2016-10-24
Applicant: Analog Devices, Inc.
Inventor： David Lamb , Khiem Quang Nguyen
CPC classification number: H03H17/0294 , H03H17/0444 , H03M3/50
Abstract: A discrete-time (e.g., digital) filter can be used as an interpolation filter for processing an oversampled input signal, such as included as a portion of a sigma-delta digital-to-analog conversion circuit. An interpolation filter control circuit can be configured to adjust a filter order of the discrete-time interpolation filter at least in part in response to information indicative of an envelope signal magnitude. For example, higher-level input signals might be processed using an interpolation filter having a stop-band attenuation that is more stringently-specified (e.g., having greater attenuation) than a corresponding attenuation used for lower-level input signals. The filter order can be variable, such as varied in response to a detected envelope magnitude of the input signal to achieve power savings as compared to a filter having fixed parameters.
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Patent Agency Ranking
6.发明授权Ultra low power dual quantizer architecture for oversampling delta-sigma modulator 有权用于过采样Δ-Σ调制器的超低功耗双量化器架构公开(公告)号：US09419642B1
公开(公告)日：2016-08-16
申请号：US14736419
申请日：2015-06-11
Applicant: ANALOG DEVICES, INC.
Inventor： Khiem Quang Nguyen
IPC: H03M3/00
Abstract: Power consumption of analog-to-digital converters (ADCs) is one important requirement for automotive and consumer devices. One flavor of an ADC is a dual quantizer architecture for oversampling delta-sigma modulators. The dual quantizer delta-sigma modulator has a first quantizer for digitizing the output of the loop filter and a second quantizer for digitizing the input of the quantizer. However, the quantization noise of the second quantizer is a highly correlated signal and significantly degrades the spectrum of the delta-sigma modulator. To address this issue, an improvement to the dual quantizer architecture is made to cancel the quantization noise of the second quantizer that is digitizing the input. Furthermore, the improvement allows the second quantizer to run at a much slower sampling rate than the first quantizer. Advantageously, the improvement provides reduction in power consumption and the overall area of modulator.
Abstract translation: 模数转换器（ADC）的功耗是汽车和消费类设备的一个重要要求。 ADC的一种风格是用于过采样delta-sigma调制器的双量化器架构。 双量化器Δ-Σ调制器具有用于数字化环路滤波器的输出的第一量化器和用于数字化量化器的输入的第二量化器。 然而，第二量化器的量化噪声是高度相关的信号，并显着降低了Δ-Σ调制器的频谱。 为了解决这个问题，对双量化器架构进行了改进以消除正在对输入进行数字化的第二量化器的量化噪声。 此外，改进允许第二量化器以比第一量化器慢得多的采样速率运行。 有利地，该改进提供功率消耗的降低和调制器的总面积。
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公开(公告)号：US10964306B2
公开(公告)日：2021-03-30
申请号：US14911239
申请日：2014-08-12
Applicant: ANALOG DEVICES, INC.
Inventor： Mikael Mortensen , Melissa Nolet , Khiem Quang Nguyen
IPC: G10K11/178 , H03M1/00
Abstract: Active Noise Cancellation (ANC) systems and methods that reduce latency to improve performance. In certain embodiments the systems sample a noise signal using a sample period to create a stream of digital signal data that is representative of the noise signal. A data transport layer carries the digital signal data to a signal processor. The transport layer temporally organizes the digital signal data to place the digital signal data within an initial phase of a sample period. The remaining phase of the sample period is set to a duration that allows the signal processor to process the digital signal data carried in the initial phase and to output the processed data during the same sample period. In this way, the processing of data occurs within one sample period and the latency is reduced and predictable.
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公开(公告)号：US09768800B1
公开(公告)日：2017-09-19
申请号：US15264421
申请日：2016-09-13
Applicant: Analog Devices, Inc.
Inventor： Khiem Quang Nguyen
CPC classification number: H03M3/50 , H03F1/0222 , H03F3/45219 , H03F3/45273 , H03F3/45475 , H03F2200/102 , H03F2200/435 , H03F2203/45154 , H03M1/124 , H03M3/322
Abstract: An apparatus comprises a digital to analog converter (DAC) circuit configured to receive a time-varying a digital input signal and convert the digital input signal to an analog output signal, an output amplifier circuit operatively coupled to the output of the DAC circuit, a peak detector circuit operatively coupled to the input the DAC and configured to produce a signal envelope of the digital input signal, and logic circuitry. The logic circuitry is operatively coupled to the peak detector circuit and is configured to detect when the signal envelope satisfies a specified threshold value; and to adjust a drive capability of an output amplifier circuit of the DAC circuit according to the signal envelope.
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公开(公告)号：US09397676B1
公开(公告)日：2016-07-19
申请号：US14868616
申请日：2015-09-29
Applicant: ANALOG DEVICES, INC.
Inventor： Khiem Quang Nguyen
CPC classification number: H03M1/002 , H03M1/0872 , H03M1/742
Abstract: Embodiments of the present disclosure provide improved switching techniques for controlling three-level DAC cells employing a return-to-hold scheme. Disclosed techniques include switching a DAC cell off for at least the duration of a time period between two hold periods while a digital value of zero is being converted. Because the DAC cell is switched off between two hold periods, the current source drain voltage is not disturbed during the critical transient times when D flip-flop outputs change, which happens during the hold periods, in response to change of digital values to be converted. In this manner, power consumption may be reduced while preserving the high performance properties of a three-level return-to-hold DAC.
Abstract translation: 本公开的实施例提供了改进的用于使用返回保持方案来控制三电平DAC单元的切换技术。 所公开的技术包括：在转换数字值为零的情况下，至少在两个保持周期之间的时间段的持续时间内关闭DAC单元。 因为DAC单元在两个保持周期之间被关断，所以在D触发器输出改变的临界瞬变时间期间电流源极漏极电压不受干扰，这在瞬时期间响应于要转换的数字值的变化而发生 。 以这种方式，可以降低功耗，同时保持三电平保持DAC的高性能。
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公开(公告)号：US20210231701A1
公开(公告)日：2021-07-29
申请号：US16751182
申请日：2020-01-23
Applicant: Analog Devices, Inc.
Inventor： Khiem Quang Nguyen , Adam R. Spirer
Abstract: Sensor apparatus and methods for operating the same for measuring acceleration are disclosed. In some embodiments, circuitry inside a sensor digitizes a measured acceleration signal from an accelerometer into a digitized acceleration signal, which is processed by a digital equalization filter within the sensor to provide an equalized acceleration signal. The equalized acceleration signal may have a frequency response that is substantially flat over a frequency range that extends beyond the resonant frequency of a MEMs sensor within the accelerometer of the sensor.
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