公开(公告)号：US06686233B2

公开(公告)日：2004-02-03

申请号：US09985447

申请日：2001-11-02

申请人： Anders Söderbärg ,  Peter Olofsson ,  Andrej Litwin

发明人： Anders Söderbärg ,  Peter Olofsson ,  Andrej Litwin

IPC分类号： H01L218238

CPC分类号： H01L29/66681 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/42368 ,  H01L29/7816

摘要： The invention relates to a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, in an n-well CMOS process by adding solely two additional process steps to a conventional CMOS process: (i) a masking step, and (ii) an ion implantation step for forming a doped channel region for the high voltage MOS transistor in the substrate self-aligned to the edge of the high voltage MOS transistor gate region. The ion implantation is performed through the mask in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create the doped channel region partly underneath the gate region of the high voltage MOS transistor.

摘要翻译： 本发明涉及一种用于在n阱CMOS工艺中分别与低电压NMOS晶体管和低电压PMOS晶体管一起形成高压NMOS晶体管的方法，其通过仅将两个额外的工艺步骤添加到传统的CMOS工艺中：（ i）掩模步骤，和（ii）离子注入步骤，用于在与高电压MOS晶体管栅极区域的边缘自对准的衬底中形成用于高电压MOS晶体管的掺杂沟道区。 离子注入通过掩模在与衬底表面的法线倾斜的方向上进行，从而在高压MOS晶体管的栅极区域的部分下方形成掺杂沟道区。

公开(公告)号：US06183857B2

公开(公告)日：2001-02-06

申请号：US09098515

申请日：1998-06-17

申请人： Andrej Litwin ,  Anders Söderbärg

发明人： Andrej Litwin ,  Anders Söderbärg

IPC分类号： B32B516

CPC分类号： H01L21/28537 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/288 ,  H01L21/76251 ,  H01L29/32 ,  H01L2924/0002 ,  Y10S977/773 ,  Y10T428/252 ,  Y10T428/256 ,  Y10T428/259 ,  H01L2924/00

摘要： A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron particles having Schottky barriers or pn-hetero-barriers and distributing the particles so that the depletion regions then produced around neighbouring particles overlap. Such particles will then deplete the silicon material from electric charge carriers. The substrate material can then be processed using the standard silicon processing methods and allows integrated circuits to be manufactured which are suitable for high frequency applications. A silicon substrate is made by sputtering a metal such as Co in a silicon wafer and then silicidizing the sputtered Co atoms by means of an annealing treatment. A top silicon wafer having a silicon dioxide layer at its bottom surface is then bonded to the sputtered layer. Finally the top wafer is thinned to provide a layer thickness suitable for the processing steps required in the manufacture of components.

摘要翻译： 基于硅的硅衬底材料具有半绝缘内部层，其将基底材料的主体与顶层隔离，其中将构建集成电路。 半绝缘层通过产生具有肖特基势垒或pn异质阻挡层的亚微米颗粒而产生，并分布颗粒，使得邻近颗粒周围产生的耗尽区重叠。 这样的颗粒将从电荷载体中消耗硅材料。 然后可以使用标准硅处理方法来处理衬底材料，并且允许制造适合于高频应用的集成电路。 通过在硅晶片中溅射诸如Co的金属，然后通过退火处理将溅射的Co原子硅化，制成硅衬底。 然后在其底表面具有二氧化硅层的顶部硅晶片接合到溅射层。 最后，顶部晶片被薄化以提供适合于组件制造中所需的加工步骤的层厚度。

公开(公告)号：US06475926B2

公开(公告)日：2002-11-05

申请号：US09737263

申请日：2000-12-13

申请人： Andrej Litwin ,  Anders Söderbärg

发明人： Andrej Litwin ,  Anders Söderbärg

IPC分类号： H01L2102

CPC分类号： H01L21/28537 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/288 ,  H01L21/76251 ,  H01L29/32 ,  H01L2924/0002 ,  Y10S977/773 ,  Y10T428/252 ,  Y10T428/256 ,  Y10T428/259 ,  H01L2924/00

摘要： A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron particles having Schotty barriers or pn-hereto-barriers and distributing X particles so that the depletion regions then produced around neighbouring particles overlap. Such particles will then deplete the silicon material from electric charge carriers. The substrate material can then be processed using the standard silicon processing methods and allows integrated circuits to be manufactured which are suitable for high frequency applications. A silicon substrate is made by sputtering a metal such as Co in a silicon wafer and then silicidizing the sputtered Co atoms by means of an annealing treatment. A top silicon wafer having a silicon dioxide layer at its bottom surface is then bonded to the sputted layer. Finally the top wafer is thinned to provide a layer thickness suitable for the processing steps required in the manufacture of components.

摘要翻译： 基于硅的硅衬底材料具有半绝缘内部层，其将基底材料的主体与顶层隔离，其中将构建集成电路。 半绝缘层是通过产生具有Schotty屏障或pn-本体 - 阻挡层并分布X颗粒的亚微米颗粒产生的，以致随后围绕相邻颗粒产生的耗尽区重叠。 这样的颗粒将从电荷载体中消耗硅材料。 然后可以使用标准硅处理方法来处理衬底材料，并且允许制造适合于高频应用的集成电路。 通过在硅晶片中溅射诸如Co的金属，然后通过退火处理将溅射的Co原子硅化，制成硅衬底。 然后将其在其底表面具有二氧化硅层的顶部硅晶片结合到该突出层。 最后，顶部晶片被薄化以提供适合于组件制造中所需的加工步骤的层厚度。

公开(公告)号：US06538294B1

公开(公告)日：2003-03-25

申请号：US09598172

申请日：2000-06-21

申请人： Håkan Sjödin ,  Anders Söderbärg

发明人： Håkan Sjödin ,  Anders Söderbärg

IPC分类号： H01L2976

CPC分类号： H01L29/0847 ,  H01L21/763 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0821 ,  H01L29/10 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/861

摘要： An arrangement in a semiconductor component includes a highly doped layer on a substrate layer and is delimited by at least one trench extending from the surface of the component through the highly doped layer. A sub-layer between the substrate layer and the highly doped layer is doped with the same type of dopant as the buried collector, but to a lower concentration. The sub-layer causes a more even distribution of the potential lines in the substrate and in a sub-collector layer, thereby eliminating areas of dense potential lines and increasing the breakdown voltage of the component, (i.e., because the breakdown voltage is lower in areas with dense potential lines).

摘要翻译： 半导体部件中的布置包括在衬底层上的高度掺杂的层，并且由从部件的表面延伸穿过高掺杂层的至少一个沟槽界定。 衬底层和高掺杂层之间的子层掺杂有与掩埋集电器相同类型的掺杂剂，但是掺杂到较低的浓度。 子层导致基板和子集电极层中的电位线更均匀分布，从而消除了致密电位线的区域并增加了元件的击穿电压（即，因为击穿电压较低 具有密集电位线的区域）。

公开(公告)号：US06326292B1

公开(公告)日：2001-12-04

申请号：US09193181

申请日：1998-11-16

申请人： Anders Söderbärg ,  Håkan Sjödin

发明人： Anders Söderbärg ,  Håkan Sjödin

IPC分类号： H01L2144

CPC分类号： H01L29/66265 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0821 ,  H01L29/66772 ,  H01L29/7809 ,  Y10S257/904

摘要： A semiconductor includes a buried conducting layer, such as a buried collector, comprises a trench, the walls of which are covered with a layer of a material in which dopant ions diffuse faster than in monocrystalline silicon. A contact area is doped in close proximity to the trench wall. The dopants will diffuse through the layer and form a low resistance connection to the buried layer. The layer may comprise polysilicon or porous silicon, or a silicide. If the material used in the layer is not in itself conducting, the size of the component may be significantly reduced.

摘要翻译： 半导体包括掩埋导电层，例如掩埋式集电器，其包括沟槽，其沟槽被一层材料覆盖，其中掺杂剂离子比单晶硅更快地扩散。 接触区域在沟壁附近被掺杂。 掺杂剂将扩散通过层并形成与埋层的低电阻连接。 该层可以包括多晶硅或多孔硅或硅化物。 如果层中使用的材料本身不导电，则组分的尺寸可能会显着降低。

公开(公告)号：US06757834B2

公开(公告)日：2004-06-29

申请号：US09826962

申请日：2001-04-06

申请人： Torbjörn Randahl ,  Albin Johansson ,  Anders Söderbärg ,  Tore André ,  Allan Olson

发明人： Torbjörn Randahl ,  Albin Johansson ,  Anders Söderbärg ,  Tore André ,  Allan Olson

IPC分类号： G06F132

CPC分类号： H04L25/028 ,  H03G3/004 ,  H04L25/0272

摘要： To minimize power dissipation in a line driver (3) in a central office (CO) for driving a DSL connection to a network terminal (NT) with a predetermined maximum constellation size, the central office (CO) supplies the line driver (3) with a predetermined supply voltage during a training sequence, and transfers data with a predetermined power spectral density in all available channels. The network terminal (NT) measures the signal-to-noise ratio of each channel, and transfers information to the central office (CO) about channels having signal-to-noise ratios that enable transfer of data. The central office (CO) reduces the power spectral density to a lowest possible value that still enables transfer of data in all channels having signal-to-noise ratios above a predetermined threshold as set by the maximum constellation size, calculates a sum of power to be transmitted in said channels, converts said sum into a corresponding line driver output voltage, and reduces the line driver supply voltage in correspondence thereto.

摘要翻译： 为了最小化用于以预定的最大星座大小驱动到网络终端（NT）的DSL连接的中心局（CO）中的线路驱动器（3）中的功率消耗，中心局（CO）提供线路驱动器（3） 在训练序列期间具有预定的电源电压，并且在所有可用信道中以预定功率谱密度传送数据。 网络终端（NT）测量每个信道的信噪比，并将关于具有使能传输数据的信噪比的信道的信息传送到中心局（CO）。 中心局（CO）将功率谱密度降低到最低可能的值，该最小可能值仍然能够传输具有由最大星座大小设定的高于预定阈值的信噪比的所有信道中的数据， 在所述通道中发送，将所述和转换成相应的线路驱动器输出电压，并且相应地降低线路驱动器电源电压。

公开(公告)号：US06300173B1

公开(公告)日：2001-10-09

申请号：US09236001

申请日：1999-01-22

申请人： Anders Söderbärg ,  Nils Ögren ,  Håkan Sjödin ,  Ivar Hamberg

发明人： Anders Söderbärg ,  Nils Ögren ,  Håkan Sjödin ,  Ivar Hamberg

IPC分类号： H01L2100

CPC分类号： H01L27/1203

摘要： A conductor 1 crossing a trench around an electrical component 1 is electrically connected to an isolated intermediate conducting region in order to move the field strength concentrations out of the electrical component and into the intermediate conducting region. This prevents avalanche breakdown occurring in the electrical component.

摘要翻译： 与电气部件1交叉的导体1电连接到隔离的中间导电区域，以便将电场强度浓度移出电气部件并进入中间导电区域。 这防止在电气部件中发生雪崩击穿。