利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

12 条记录 (耗时 0.014 秒)

    Method and device relating to semiconductor components
    1.
    发明授权
    Method and device relating to semiconductor components 有权
    涉及半导体元件的方法和装置

    公开(公告)号：US06300173B1

    公开(公告)日：2001-10-09

    申请号：US09236001

    申请日：1999-01-22

    申请人： Anders Söderbärg ,  Nils Ögren ,  Håkan Sjödin ,  Ivar Hamberg

    发明人： Anders Söderbärg ,  Nils Ögren ,  Håkan Sjödin ,  Ivar Hamberg

    IPC分类号： H01L2100

    CPC分类号： H01L27/1203

    摘要： A conductor 1 crossing a trench around an electrical component 1 is electrically connected to an isolated intermediate conducting region in order to move the field strength concentrations out of the electrical component and into the intermediate conducting region. This prevents avalanche breakdown occurring in the electrical component.

    摘要翻译： 与电气部件1交叉的导体1电连接到隔离的中间导电区域，以便将电场强度浓度移出电气部件并进入中间导电区域。 这防止在电气部件中发生雪崩击穿。

    Trenched semiconductor device with high breakdown voltage
    2.
    发明授权
    Trenched semiconductor device with high breakdown voltage 有权
    具有高击穿电压的半导体器件

    公开(公告)号：US06538294B1

    公开(公告)日：2003-03-25

    申请号：US09598172

    申请日：2000-06-21

    申请人： Håkan Sjödin ,  Anders Söderbärg

    发明人： Håkan Sjödin ,  Anders Söderbärg

    IPC分类号： H01L2976

    CPC分类号： H01L29/0847 ,  H01L21/763 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0821 ,  H01L29/10 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/861

    摘要： An arrangement in a semiconductor component includes a highly doped layer on a substrate layer and is delimited by at least one trench extending from the surface of the component through the highly doped layer. A sub-layer between the substrate layer and the highly doped layer is doped with the same type of dopant as the buried collector, but to a lower concentration. The sub-layer causes a more even distribution of the potential lines in the substrate and in a sub-collector layer, thereby eliminating areas of dense potential lines and increasing the breakdown voltage of the component, (i.e., because the breakdown voltage is lower in areas with dense potential lines).

    摘要翻译： 半导体部件中的布置包括在衬底层上的高度掺杂的层，并且由从部件的表面延伸穿过高掺杂层的至少一个沟槽界定。 衬底层和高掺杂层之间的子层掺杂有与掩埋集电器相同类型的掺杂剂，但是掺杂到较低的浓度。 子层导致基板和子集电极层中的电位线更均匀分布，从而消除了致密电位线的区域并增加了元件的击穿电压（即，因为击穿电压较低 具有密集电位线的区域）。

    Semiconductor component and manufacturing method for semiconductor component
    3.
    发明授权
    Semiconductor component and manufacturing method for semiconductor component 失效
    半导体元件半导体元件及制造方法

    公开(公告)号：US06326292B1

    公开(公告)日：2001-12-04

    申请号：US09193181

    申请日：1998-11-16

    申请人： Anders Söderbärg ,  Håkan Sjödin

    发明人： Anders Söderbärg ,  Håkan Sjödin

    IPC分类号： H01L2144

    CPC分类号： H01L29/66265 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0821 ,  H01L29/66772 ,  H01L29/7809 ,  Y10S257/904

    摘要： A semiconductor includes a buried conducting layer, such as a buried collector, comprises a trench, the walls of which are covered with a layer of a material in which dopant ions diffuse faster than in monocrystalline silicon. A contact area is doped in close proximity to the trench wall. The dopants will diffuse through the layer and form a low resistance connection to the buried layer. The layer may comprise polysilicon or porous silicon, or a silicide. If the material used in the layer is not in itself conducting, the size of the component may be significantly reduced.

    摘要翻译： 半导体包括掩埋导电层，例如掩埋式集电器，其包括沟槽，其沟槽被一层材料覆盖，其中掺杂剂离子比单晶硅更快地扩散。 接触区域在沟壁附近被掺杂。 掺杂剂将扩散通过层并形成与埋层的低电阻连接。 该层可以包括多晶硅或多孔硅或硅化物。 如果层中使用的材料本身不导电，则组分的尺寸可能会显着降低。

    ESL LOCKING MECHANISM
    4.
    发明申请
    ESL LOCKING MECHANISM 有权
    ESL锁定机构

    公开(公告)号：US20120023797A1

    公开(公告)日：2012-02-02

    申请号：US13257460

    申请日：2010-03-09

    申请人： Pär Rosander ,  Håkan Sjödin ,  Nils Hulth ,  Daniel Ekfjorden ,  Elias Svensson ,  Kenneth Ellingsen ,  Torsten Freyhall ,  Eirik Lundmark ,  Anders Nilsson ,  Maral Babapour ,  Ines Junge

    发明人： Pär Rosander ,  Håkan Sjödin ,  Nils Hulth ,  Daniel Ekfjorden ,  Elias Svensson ,  Kenneth Ellingsen ,  Torsten Freyhall ,  Eirik Lundmark ,  Anders Nilsson ,  Maral Babapour ,  Ines Junge

    IPC分类号： G09F3/08

    CPC分类号： G09F3/204

    摘要： An ESL and ESL holder combination includes a locking mechanism for releasably securing the ESL to the ESL holder, and an ESL provided with at least one gripping means for cooperative engagement with the ESL holder. The ESL holder is attachable to an edge of a shelf, the ESL holder being provided with one or more receiving means such as for example slots for receiving the gripping means and the locking element in cooperative engagement. A spring loaded element is arranged inside the ESL such that the spring loaded element, in a latched position, secures the ESL to the ESL holder when the gripping means is brought into a hooked position in the receiving means. When displaced from its latched position, allowing the gripping means to leave its hooked position, this enables removal of the ESL from the ESL holder.

    摘要翻译： ESL和ESL保持器组合包括用于将ESL可释放地固定到ESL保持器的锁定机构，以及设置有至少一个夹持装置以与ESL保持器协作接合的ESL。 ESL保持器可附接到搁板的边缘，ESL保持器设置有一个或多个接收装置，例如用于接合夹持装置和锁定元件协作接合的槽。 弹簧加载元件设置在ESL内部，使得当夹持装置在接收装置中处于钩状位置时，处于闩锁位置的弹簧加载元件将ESL固定到ESL保持器。 当从其锁定位置移位时，允许夹持装置离开其钩状位置，这样可以将ESL从ESL夹持器上移除。

    ESL locking mechanism
    6.
    发明授权
    ESL locking mechanism 有权
    ESL锁定机制

    公开(公告)号：US08627588B2

    公开(公告)日：2014-01-14

    申请号：US13257460

    申请日：2010-03-09

    申请人： Pär Rosander ,  Håkan Sjödin ,  Nils Hulth ,  Daniel Ekfjorden ,  Elias Svensson ,  Kenneth Ellingsen ,  Torsten Frey-Hall ,  Eirik Lundmark ,  Anders Nilsson ,  Maral Babapour ,  Ines Junge

    发明人： Pär Rosander ,  Håkan Sjödin ,  Nils Hulth ,  Daniel Ekfjorden ,  Elias Svensson ,  Kenneth Ellingsen ,  Torsten Frey-Hall ,  Eirik Lundmark ,  Anders Nilsson ,  Maral Babapour ,  Ines Junge

    IPC分类号： G09F3/18

    CPC分类号： G09F3/204

    摘要： An ESL and ESL holder combination includes a locking mechanism for releasably securing the ESL to the ESL holder, and an ESL provided with at least one gripping means for cooperative engagement with the ESL holder. The ESL holder is attachable to an edge of a shelf, the ESL holder being provided with one or more receiving means such as for example slots for receiving the gripping means and the locking element in cooperative engagement. A spring loaded element is arranged inside the ESL such that the spring loaded element, in a latched position, secures the ESL to the ESL holder when the gripping means is brought into a hooked position in the receiving means. When displaced from its latched position, allowing the gripping means to leave its hooked position, this enables removal of the ESL from the ESL holder.

    摘要翻译： ESL和ESL保持器组合包括用于将ESL可释放地固定到ESL保持器的锁定机构，以及设置有至少一个夹持装置以与ESL保持器协作接合的ESL。 ESL保持器可附接到搁板的边缘，ESL保持器设置有一个或多个接收装置，例如用于接合夹持装置和锁定元件协作接合的槽。 弹簧加载元件设置在ESL内部，使得当夹持装置在接收装置中处于钩状位置时，处于闩锁位置的弹簧加载元件将ESL固定到ESL保持器。 当从其锁定位置移位时，允许夹持装置离开其钩状位置，这样可以将ESL从ESL夹持器上移除。

    Semiconductor circuit regulator
    8.
    发明授权
    Semiconductor circuit regulator 有权
    半导体电路调节器

    公开(公告)号：US07098723B2

    公开(公告)日：2006-08-29

    申请号：US10470520

    申请日：2002-01-25

    申请人： Henrik Hellberg ,  Anders Emericks ,  Håkan Sjödin

    发明人： Henrik Hellberg ,  Anders Emericks ,  Håkan Sjödin

    IPC分类号： H03K3/01 ,  G05F1/10 ,  G05F3/02

    CPC分类号： H04M3/005 ,  H04M2201/06

    摘要： In a circuit designed to output a varying output voltage, the substrate of the semi-conductor component is connected to a regulator, in particular a switch, connected to a lower potential than the potential of the substrate of the circuit. The circuit can for example be used in a Subscriber Line Interface Circuit (SLIC).

    摘要翻译： 在设计成输出变化的输出电压的电路中，半导体部件的基板连接到调节器，特别是开关，其连接到比电路的基板的电位更低的电位。 该电路可以例如在用户线路接口电路（SLIC）中使用。

    Method and system for improving a transistor model
    10.
    发明授权
    Method and system for improving a transistor model 失效
    改善晶体管模型的方法和系统

    公开(公告)号：US06532438B2

    公开(公告)日：2003-03-11

    申请号：US09200605

    申请日：1998-11-30

    申请人： Håkan Sjödin ,  Hans Hjelmgren ,  Lars-Peter Jacobson ,  Anders Eklund

    发明人： Håkan Sjödin ,  Hans Hjelmgren ,  Lars-Peter Jacobson ,  Anders Eklund

    IPC分类号： G06F1750

    CPC分类号： G01R31/2846 ,  G06F17/5036

    摘要： An improved system for simulating bipolar transistors with a variation in Early voltage as a function of collector/emitter bias voltage is disclosed. The simulation is based upon a standard Gummel-Poon model and is improved by an Early voltage extension, where the constant Early voltage is replaced by an Early voltage that is divided into several regions. The Early voltage is adjusted to fit the actual variations of the measured Early voltage characteristics of a bipolar transistor. The Early voltage within each region is used for calculating the bipolar transistors base charge which then is used to simulate the performance of the bipolar transistor. The regions may be linked together by choice of boundary conditions.

    摘要翻译： 公开了一种用于模拟具有作为集电极/发射极偏置电压的函数的早期电压变化的双极晶体管的改进的系统。 该模拟基于标准的Gummel-Poon模型，并通过早期电压延长进行改进，其中恒定的早期电压被分为几个区域的早期电压代替。 早期电压被调节以适应双极晶体管的测量的早期电压特性的实际变化。 每个区域内的早期电压用于计算双极晶体管基极电荷，然后用于模拟双极晶体管的性能。 这些区域可以通过边界条件的选择来连接在一起。