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公开(公告)号：US06552396B1
公开(公告)日：2003-04-22
申请号：US09524295
申请日：2000-03-14
IPC分类号： H01L2701
CPC分类号： H01L27/1203 , H01L21/84
摘要： An SOI multiple FET structure is provided that comprises a substrate having a substrate layer on an insulator layer. The SOI multiple FET structure includes distal diffusion regions in the substrate layer and a central diffusion region in the substrate layer. The central diffusion region has a width and extends from a surface of the substrate layer downward into contact with the insulator layer along a portion of the width and extends only partially into the substrate layer along another portion of the width. The SOI multiple FET structure also includes a pair of gates on the surface of the substrate layer each overlapping one of the distal diffusion regions and the central diffusion region; and a pair of body regions in the substrate layer each under one of the gates for forming a channel between the one of the distal diffusion regions and the central diffusion region. The body regions are in electrical communication under the another portion of the width of the central diffusion region. Methods for forming the SOI multiple FET structure are also provided.
摘要翻译： 提供了SOI多FET结构，其包括在绝缘体层上具有衬底层的衬底。 SOI多FET结构包括衬底层中的远端扩散区域和衬底层中的中心扩散区域。 中心扩散区具有宽度并且从衬底层的表面向下延伸，沿着宽度的一部分与绝缘体层接触，并且沿宽度的另一部分仅部分地延伸到衬底层中。 SOI多FET结构还包括在衬底层的表面上的一对栅极，每个栅极重叠远端扩散区域和中心扩散区域之一; 以及在所述基板层中的一个所述栅极之间的一对体区，用于在所述远侧扩散区域和所述中央扩散区域中的一个之间形成沟道。 身体区域在中央扩散区域的宽度的另一部分下电连通。 还提供了形成SOI多FET结构的方法。
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公开(公告)号：US06333230B1
公开(公告)日：2001-12-25
申请号：US09571055
申请日：2000-05-15
IPC分类号： H01L21336
CPC分类号： H01L29/66621 , H01L21/2251 , H01L29/7834
摘要： A method of fabricating a semiconductor device comprising: forming a trench on the face of a silicon substrate of a first conductivity type; depositing a conformal silicon layer of a second conductivity type into the trench; etching away the silicon layer of a second conductivity type selectively to leave portions of the silicon layer in the trench; annealing to drive dopant from the portions of the silicon layer through the walls of the trench into adjacent areas of the silicon substrate; and forming a gate structure in the trench, and source and drain diffusion regions in said silicon substrate on opposing sides of said gate structure.
摘要翻译： 一种制造半导体器件的方法，包括：在第一导电类型的硅衬底的表面上形成沟槽; 将第二导电类型的共形硅层沉积到沟槽中; 蚀刻掉第二导电类型的硅层以选择性地留下沟槽中的硅层的部分; 退火以将掺杂剂从硅层的部分通过沟槽的壁驱动到硅衬底的相邻区域中; 以及在所述沟槽中形成栅极结构，以及在所述硅衬底中在所述栅极结构的相对侧上的源极和漏极扩散区域。
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公开(公告)号：US06475838B1
公开(公告)日：2002-11-05
申请号：US09525103
申请日：2000-03-14
IPC分类号： H01L2162
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/0629 , H01L27/0805 , H01L27/1203 , H01L29/66772 , H01L29/78612 , H01L29/94
摘要： A decoupling capacitor and methods for forming the same are provided. In a first aspect, the decoupling capacitor is formed during a process for forming first and second type FETs on a common substrate that comprises a plurality of implant steps for doping channels and diffusions of the first and second type FETs. In a second aspect, a method is provided for forming the novel decoupling capacitor that includes the steps of forming a mandrel layer on a substrate, including forming openings in the mandrel layer and disposing a first type dopant into the substrate through the openings. Thereafter, an epitaxial layer is formed in the openings on the substrate, an insulator layer is formed in the openings on the epitaxial layer and a gate is formed in the openings on the insulator layer. The mandrel layer is removed and the first type dopant is disposed into the substrate abutting the first type dopant in the substrate that was disposed through the openings. During this step the first type dopant is disposed into the gate. The substrate having the first type dopant comprises one terminal of the capacitor and the gate comprises another terminal of the capacitor.
摘要翻译： 提供去耦电容器及其形成方法。 在第一方面，去耦电容器在用于在公共衬底上形成第一和第二类型FET的工艺中形成，该公共衬底包括用于掺杂第一和第二类型FET的沟道和扩散的多个注入步骤。 在第二方面，提供了一种用于形成新型去耦电容器的方法，该方法包括以下步骤：在基底上形成心轴层，包括在心轴层中形成开口，并通过开口将第一类型掺杂剂设置到基底中。 此后，在衬底上的开口中形成外延层，在外延层的开口中形成绝缘体层，并在绝缘体层的开口中形成栅极。 去除心轴层，并且将第一类型掺杂剂设置在与通过开口设置的衬底中邻接第一类型掺杂剂的衬底中。 在该步骤期间，将第一类型的掺杂剂设置在栅极中。 具有第一类型掺杂物的衬底包括电容器的一个端子，并且栅极包括电容器的另一个端子。
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公开(公告)号：US06469350B1
公开(公告)日：2002-10-22
申请号：US09682868
申请日：2001-10-26
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L21/743 , H01L29/66545 , H01L29/78612 , H01L29/78618 , Y10S148/077 , Y10S148/15
摘要： A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes field effect transistor 124 comprising at least body region 127 and diffusion regions 132; buried interconnect plane 122 optionally self-aligned to diffusion regions 132 and in contact with body region 127; isolation oxide region 118 between diffusion regions 132 and buried interconnect plane 122; and buried oxide layer 104 present beneath buried interconnect plane 122.
摘要翻译： 本文公开了在绝缘体上硅衬底上制造并具有活性阱方案的半导体器件以及制造这种器件的包括非自对准和自对准的方法。 半导体器件包括至少包括体区127和扩散区132的场效应晶体管124; 埋入的互连平面122可选地与扩散区132自对准并与体区127接触; 扩散区域132和掩埋互连平面122之间的隔离氧化物区域118; 和掩埋的互连平面122下方的掩埋氧化物层104。
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公开(公告)号：US06664150B2
公开(公告)日：2003-12-16
申请号：US10205528
申请日：2002-07-25
IPC分类号： H01L2100
CPC分类号： H01L29/66772 , H01L21/743 , H01L29/66545 , H01L29/78612 , H01L29/78618 , Y10S148/077 , Y10S148/15
摘要： A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes field effect transistor 124 comprising at least body region 127 and diffusion regions 132; buried interconnect plane 122 optionally self-aligned to diffusion regions 132 and in contact with body region 127; isolation oxide region 118 between diffusion regions 132 and buried interconnect plane 122; and buried oxide layer 104 present beneath buried interconnect plane 122.
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公开(公告)号：US6100564A
公开(公告)日：2000-08-08
申请号：US163950
申请日：1998-09-30
申请人： Andres Bryant , Edward J. Nowak , Minh H. Tong
发明人： Andres Bryant , Edward J. Nowak , Minh H. Tong
CPC分类号： H01L27/0288 , H01L21/84 , H01L27/1203 , H01L2924/0002
摘要： An SOI pass-gate disturb solution for an N-type MOSFET wherein a resistor is connected between the gate and the body of the FET to eliminate the disturb condition. The FET is fabricated in a substrate having a source, a drain and a gate, wherein the body of the field effect transistor is electrically floating and the transistor is substantially electrically isolated from the substrate. A high resistance path is provided coupling the electrically floating body of the FET to the gate, such that the body discharges to a low state before significant thermal charging can occur when the gate is low, and thus prevents the accumulation of a charge on the body when the transistor is off. The resistance of the high resistance path is preferably approximately 10.sup.10 Ohms-um divided by the width of the pass-gate.
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公开(公告)号：US5959335A
公开(公告)日：1999-09-28
申请号：US159307
申请日：1998-09-23
申请人： Andres Bryant , William F. Clark , John J. Ellis-Monaghan , Edward P. Maciejewski , Edward J. Nowak , Wilbur D. Pricer , Minh H. Tong
发明人： Andres Bryant , William F. Clark , John J. Ellis-Monaghan , Edward P. Maciejewski , Edward J. Nowak , Wilbur D. Pricer , Minh H. Tong
IPC分类号： H01L27/06 , H01L21/8234 , H01L27/12 , H01L29/78 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7841 , H01L27/1203
摘要： A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.
摘要翻译： 用于SOI CMOS中的FET的器件设计，其被设计用于当FET导通时增强通过器件的电流的雪崩倍增，并且当FET关闭时去除体电荷。 FET具有电浮动体并且与衬底基本上电隔离。 本发明提供了将FET的浮体耦合到FET的源极的高电阻路径，使得该电阻器使得该器件能够充当用于有源开关目的的浮动体并且作为待机模式中的接地体以减少 漏电流。 高电阻路径具有至少1MΩ的电阻，并且包括通过使用分离多晶硅工艺制造的多晶硅电阻器，其中掩埋接触掩模在第一多晶硅层中打开孔，以允许第二多晶硅层 接触基板。
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公开(公告)号：US06437594B1
公开(公告)日：2002-08-20
申请号：US09528350
申请日：2000-03-17
申请人： Ronald J. Bolam , Andres Bryant , Edward J. Nowak , Minh H. Tong
发明人： Ronald J. Bolam , Andres Bryant , Edward J. Nowak , Minh H. Tong
IPC分类号： G01R2722
CPC分类号： G01R31/3004
摘要： A monitor for detecting pass gate leakage in a silicon on insulator device and a method for using the same is described herein. A pulse generator supplies a signal to a set of buffers connected in parallel, which pass on a signal to the source side of a series of NFETs. The plurality of NFETs are ordered by increasing channel widths. The NFETs have grounded gates, and therefore will not pass current due to field effects. Each NFET is connected to a latch, and the latches are originally set to the same state. When the signal supplied to the NFET drops from high to low, pass gate leakage will occur through the channel of each NFET. If pass gate leakage through any given NFET is sufficient, the latch will change states. The latch output signal is sent to a shift register, which can be made to output information. By incorporating the monitor on the chip, pass gate leakage tolerances and specifications can be established in-line during manufacture.
摘要翻译： 这里描述了一种用于检测绝缘体上硅器件中的漏极泄漏的监视器及其使用方法。 脉冲发生器将信号提供给并联连接的一组缓冲器，该缓冲器将信号传递到一系列NFET的源极侧。 通过增加通道宽度来排列多个NFET。 NFET具有接地栅极，因此由于场效应而不会通过电流。 每个NFET连接到一个锁存器，并且锁存器最初设置为相同的状态。 当提供给NFET的信号从高到低时，通过每个NFET的通道将发生栅极泄漏。 如果通过任何给定NFET的漏极泄漏就足够了，锁存器将改变状态。 锁存器输出信号发送到移位寄存器，可以输出信息。 通过将显示器结合在芯片上，可以在制造过程中在线建立传递门泄漏公差和规格。
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公开(公告)号：US06200843B1
公开(公告)日：2001-03-13
申请号：US09159841
申请日：1998-09-24
申请人： Andres Bryant , Edward J. Nowak , Minh H. Tong
发明人： Andres Bryant , Edward J. Nowak , Minh H. Tong
IPC分类号： H01L218238
CPC分类号： H01L29/42368 , H01L21/28167 , H01L21/28194 , H01L21/823857 , H01L27/092 , Y10S438/981
摘要： A method for forming a semiconductor device. A substrate is provided. A first electrically insulating layer is formed on the substrate. A second electrically insulating layer is formed on the first electrically insulating layer. Openings are formed through the second electrically insulating layer down to the level of the first electrically insulating layer. Spacers are formed on opposing sidewalls of the openings. The spacers on one of the opposing side walls of the openings are removed, thereby exposing portions of the first electrically insulating layer. Exposed portions of the first electrically insulating layer in the openings are removed, thereby exposing portions of the substrate. The spacers on another of the opposing sidewalls of the openings are removed, thereby exposing portions of the first electrically insulating layer. A third electrically insulating layer is formed in the openings over the exposed portions of the first electrically insulating layer and the exposed portions of the substrate.
摘要翻译： 一种形成半导体器件的方法。 提供基板。 在基板上形成第一电绝缘层。 在第一电绝缘层上形成第二电绝缘层。 通过第二电绝缘层形成通向第一电绝缘层的水平面的开口。 间隔件形成在开口的相对侧壁上。 去除开口的一个相对侧壁上的间隔件，从而暴露第一电绝缘层的部分。 去除开口中的第一电绝缘层的暴露部分，从而暴露基板的部分。 去除开口的另一相对侧壁上的间隔物，从而暴露第一电绝缘层的部分。 在第一电绝缘层的暴露部分和基板的暴露部分的开口中形成第三电绝缘层。
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公开(公告)号：US06249028B1
公开(公告)日：2001-06-19
申请号：US09175308
申请日：1998-10-20
申请人： Andres Bryant , Edward J. Nowak , Minh H. Tong
发明人： Andres Bryant , Edward J. Nowak , Minh H. Tong
IPC分类号： H01L2900
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L29/42384 , H01L29/66825
摘要： An FET structure for utilization with a silicon-on-insulator semiconductor device structure. The structure includes a silicon-on-insulator substrate structure. Source and drain diffusion regions are provided on the silicon-on-insulator substrate. An FET body region is interconnected with the source and drain diffusion regions. A gate oxide region is arranged over at least a portion of the body region and the source and drain diffusion regions. A gate region is arranged over at least a portion of the gate oxide region. A diode is interconnected with and provides a conductive pathway between the gate region and the FET body region. The diode is electrically isolated from the FET source and drain regions and inversion channel by a high threshold FET region.
摘要翻译： 一种利用绝缘体上硅半导体器件结构的FET结构。 该结构包括绝缘体上硅衬底结构。 源极和漏极扩散区域设置在绝缘体上硅衬底上。 FET体区域与源极和漏极扩散区域互连。 栅极氧化物区域布置在主体区域和源极和漏极扩散区域的至少一部分上。 栅极区域布置在栅极氧化物区域的至少一部分上。 二极管与栅极区域和FET体区域互连并提供导电通路。 二极管通过高阈值FET区域与FET源极和漏极区域和反向沟道电隔离。
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