公开(公告)号：US07804107B1

公开(公告)日：2010-09-28

申请号：US11906619

申请日：2007-10-03

申请人： Andrew E. Horch ,  Fred Hause

发明人： Andrew E. Horch ,  Fred Hause

IPC分类号： H01L31/111

CPC分类号： H01L21/84 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/1027 ,  H01L27/1203 ,  H01L29/66378

摘要： In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask. Epitaxial material may then be formed selectively over exposed regions of the semiconductor material as defined by the silicide-blocking mask. Silicide might also be formed after select exposed regions as defined by the silicide-blocking mask. The silicide-blocking mask may thus be used for alignment of implants, and also for defining epitaxial and silicide alignments.

摘要翻译： 在半导体器件的处理方法中，可以在半导体材料上形成硅化物阻挡层。 在限定硅化物阻挡层之后，可以将杂质注入半导体材料的部分，如由硅化物阻挡层所限定的。 在植入之后，硅化物可以形成在半导体材料的表面区域，如硅化物阻挡层所允许的。 杂质植入物的区域可以包括与其上形成的硅化物的轮廓相关的边界。 在另一实施例中，植入物可以限定到晶闸管器件的基极区域。 可以以入射角来执行植入物，以将阻挡掩模的外围边缘下方的基底区域的部分延伸。 接下来，可以使用基本上正交的入射角并与掩模自对准的植入物形成阳极 - 发射极区域。 然后可以在由硅化物阻挡掩模限定的半导体材料的暴露区域上选择性地形成外延材料。 也可以在由硅化物阻挡掩模定义的选择的暴露区域之后形成硅化物。 硅化物阻挡掩模因此可用于植入物的对准，并且还用于限定外延和硅化物对准。

公开(公告)号：US06888176B1

公开(公告)日：2005-05-03

申请号：US10609185

申请日：2003-06-26

申请人： Andrew E. Horch ,  Fred Hause

发明人： Andrew E. Horch ,  Fred Hause

IPC分类号： H01L21/332 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/66393 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41716 ,  H01L29/7436

摘要： In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask. Epitaxial material may then be formed selectively over exposed regions of the semiconductor material as defined by the silicide-blocking mask. Silicide might also be formed after select exposed regions as defined by the silicide-blocking mask. The silicide-blocking mask may thus be used for alignment of implants, and also for defining epitaxial and silicide alignments.

摘要翻译： 在半导体器件的处理方法中，可以在半导体材料上形成硅化物阻挡层。 在限定硅化物阻挡层之后，可以将杂质注入半导体材料的部分，如由硅化物阻挡层所限定的。 在植入之后，硅化物可以形成在半导体材料的表面区域，如硅化物阻挡层所允许的。 杂质植入物的区域可以包括与其上形成的硅化物的轮廓相关的边界。 在另一实施例中，植入物可以限定到晶闸管器件的基极区域。 可以以入射角来执行植入物，以将阻挡掩模的外围边缘下方的基底区域的部分延伸。 接下来，可以使用基本上正交的入射角并与掩模自对准的植入物形成阳极 - 发射极区域。 然后可以在由硅化物阻挡掩模限定的半导体材料的暴露区域上选择性地形成外延材料。 也可以在由硅化物阻挡掩模定义的选择的暴露区域之后形成硅化物。 硅化物阻挡掩模因此可用于植入物的对准，并且还用于限定外延和硅化物对准。

公开(公告)号：US07279367B1

公开(公告)日：2007-10-09

申请号：US11007510

申请日：2004-12-07

申请人： Andrew E. Horch ,  Fred Hause

发明人： Andrew E. Horch ,  Fred Hause

IPC分类号： H01L21/332

CPC分类号： H01L21/84 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/1027 ,  H01L27/1203 ,  H01L29/66378

摘要： In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask. Epitaxial material may then be formed selectively over exposed regions of the semiconductor material as defined by the silicide-blocking mask. Silicide might also be formed after select exposed regions as defined by the silicide-blocking mask. The silicide-blocking mask may thus be used for alignment of implants, and also for defining epitaxial and silicide alignments.

摘要翻译： 在半导体器件的处理方法中，可以在半导体材料上形成硅化物阻挡层。 在限定硅化物阻挡层之后，可以将杂质注入半导体材料的部分，如由硅化物阻挡层所限定的。 在植入之后，硅化物可以形成在半导体材料的表面区域，如硅化物阻挡层所允许的。 杂质植入物的区域可以包括与其上形成的硅化物的轮廓相关的边界。 在另一实施例中，植入物可以限定到晶闸管器件的基极区域。 可以以入射角来执行植入物，以将阻挡掩模的外围边缘下方的基底区域的部分延伸。 接下来，可以使用基本上正交的入射角并与掩模自对准的植入物形成阳极 - 发射极区域。 然后可以在由硅化物阻挡掩模限定的半导体材料的暴露区域上选择性地形成外延材料。 也可以在由硅化物阻挡掩模定义的选择的暴露区域之后形成硅化物。 硅化物阻挡掩模因此可用于植入物的对准，并且还用于限定外延和硅化物对准。

公开(公告)号：US08829588B2

公开(公告)日：2014-09-09

申请号：US13191223

申请日：2011-07-26

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L29/788 ,  H01L29/51 ,  H01L21/28

CPC分类号： H01L29/513 ,  G11C16/0408 ,  H01L21/28273 ,  H01L29/7881

摘要： Embodiments relate to a nonvolatile memory (“NVM”) bitcell with a replacement metal control gate and an additional floating gate. The bitcell may be created using a standard complementary metal-oxide-semiconductor manufacturing processes (“CMOS processes”) without any additional process steps, thereby reducing the cost and time associated with fabricating a semiconductor device incorporating the NVM bitcell.

摘要翻译： 实施例涉及具有替换金属控制栅极和附加浮动栅极的非易失性存储器（“NVM”）位单元。 可以使用标准互补金属氧化物半导体制造工艺（“CMOS工艺”）而不需要任何额外的工艺步骤来产生位单元，从而降低与组装NVM位单元的半导体器件制造相关的成本和时间。

公开(公告)号：US08194468B2

公开(公告)日：2012-06-05

申请号：US13158002

申请日：2011-06-10

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5621 ,  G11C16/0441 ,  G11C16/10

摘要： A Non-Volatile Memory (NVM) cell and programming method in which the cell can denote at least two logic levels (e.g., 0 and 1) and includes a read-transistor with a floating gate and a Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read transistor.The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased so that it is in accumulation, to set at least one of the logic levels.

摘要翻译： 非易失性存储器（NVM）单元和编程方法，其中单元可以表示至少两个逻辑电平（例如，0和1），并且包括具有浮置栅极和带对带隧穿装置的读晶体管 （BTBT器件）与读取晶体管共享浮动栅极。 BTBT装置被配置为当BTBT装置被偏置使得其被积累时将第一电荷注入到浮动栅上的注入装置，以设置至少一个逻辑电平。

公开(公告)号：US20090170260A1

公开(公告)日：2009-07-02

申请号：US12403333

申请日：2009-03-12

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L21/8239

CPC分类号： G11C16/12

摘要： Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes a second transistor having a second gate dielectric located between the gate electrode and the semiconductor substrate. A band-to-band tunneling current flows between valence and conduction bands of the second transistor to create a second injection current that flows through the second gate dielectric to establish the first amount of electrical charge on the gate electrode. Non-volatile memory cell circuits having the above described circuitry are also described.

摘要翻译： 电子电路被描述为具有位于电浮置栅极和半导体衬底之间的第一栅极电介质的第一晶体管。 第一注入电流流过第一栅极电介质以在栅电极上建立第一量的电荷。 电子电路还包括具有位于栅电极和半导体衬底之间的第二栅极电介质的第二晶体管。 带间隧穿电流在第二晶体管的价带和导带之间流动，以产生流过第二栅极电介质的第二注入电流，以在栅电极上建立第一量的电荷。 还描述了具有上述电路的非易失性存储单元电路。

公开(公告)号：US07456439B1

公开(公告)日：2008-11-25

申请号：US10884337

申请日：2004-07-01

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L29/74

CPC分类号： H01L29/0657 ,  G11C11/39 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/763 ,  H01L27/0617 ,  H01L27/0817 ,  H01L27/1027 ,  H01L27/1052 ,  H01L29/66363 ,  H01L29/74

摘要： A semiconductor device may comprise a plurality of memory cells. A memory cell may comprise a thyristor, at least a portion of which is formed in a pillar of semiconductor material. The pillar may comprise sidewalls defining a cylindrical circumference of a first diameter. In a particular embodiment, the pillars associated with the plurality of memory cells may define rows and columns of an array. In a further embodiment, a pillar may be spaced by a first distance of magnitude up to the first diameter relative to a neighboring pillar within its row. In an additional further embodiment, the pillar may be spaced by a second distance of a magnitude up to twice the first diameter, relative to a neighboring pillar within its column.

摘要翻译： 半导体器件可以包括多个存储单元。 存储单元可以包括晶闸管，其至少一部分形成在半导体材料的柱中。 支柱可以包括限定第一直径的圆柱形圆周的侧壁。 在特定实施例中，与多个存储器单元相关联的支柱可以定义阵列的行和列。 在另一实施例中，柱可以相对于其行内的相邻支柱间隔第一距离直到第一直径。 在另外的另外的实施例中，柱可以相对于其柱内的相邻柱而间隔第二距离，该距离的幅度高达第一直径的两倍。

公开(公告)号：US07400255B2

公开(公告)日：2008-07-15

申请号：US11069515

申请日：2005-02-28

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： G08B13/14

CPC分类号： B07C5/344 ,  G01R31/01 ,  G01R31/2822 ,  H01L2223/6677 ,  Y10T29/49004

摘要： Wirelessly testing an RFID tag before it is packaged or otherwise entered into a process reserved for “working” RFID tags is described. Various processes that employ such wireless testing as well as various “on-die” RFID tag antenna designs for facilitating the wireless testing are also described.

摘要翻译： 在将RFID标签封装或以其他方式输入到为“工作”RFID标签保留的过程中进行无线测试时，将进行描述。 还描述了采用这种无线测试的各种过程以及用于促进无线测试的各种“裸片”RFID标签天线设计。

公开(公告)号：US07256430B1

公开(公告)日：2007-08-14

申请号：US11303228

申请日：2005-12-15

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L29/74

CPC分类号： H01L29/7408 ,  H01L29/7436

摘要： A thyristor memory device may comprise a capacitor electrode formed over a base region of the thyristor using a replacement gate process. During formation of the thyristor, a base-emitter boundary may be aligned relative to a shoulder of the capacitor electrode. In a particular embodiment, the replacement gate process may comprise defining a trench in a layer of dielectric over semiconductor material. Conductive material for the electrode may be formed over the dielectric and in the trench. It may further be patterned to form a shoulder for the electrode that extends over regions of the dielectric over a base region for the thyristor. The extent of the shoulder may be used to pattern the dielectric and/or to assist alignment of implants for the base and emitter regions of the thyristor.

摘要翻译： 晶闸管存储器件可以包括使用替换栅极工艺在晶闸管的基极区域上形成的电容器电极。 在晶闸管的形成期间，基极 - 发射极边界可以相对于电容器电极的台肩对准。 在特定实施例中，替换栅极工艺可以包括在半导体材料上的介电层中限定沟槽。 用于电极的导电材料可以形成在电介质和沟槽中。 可以进一步图案化以形成电极的肩部，该电极在用于晶闸管的基极区域上的电介质的区域上延伸。 可以使用肩部的程度来图案化电介质和/或辅助晶闸管的基极和发射极区域的植入物的对准。

公开(公告)号：US20130193498A1

公开(公告)日：2013-08-01

申请号：US13361796

申请日：2012-01-30

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L27/06

CPC分类号： H01L27/11521 ,  G06F17/5072 ,  G06F17/5077 ,  G11C16/0408 ,  H01L27/11519 ,  H01L27/11558 ,  H01L28/60 ,  H01L29/42324 ,  H01L29/7833 ,  H01L29/7881

摘要： A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.