公开(公告)号：US5987600A

公开(公告)日：1999-11-16

申请号：US851140

申请日：1997-05-05

申请人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

发明人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3865 ,  G06F9/3842 ,  G06F9/3863

摘要： A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to processes the exception if the exception is indicated by one of the exception data values. The processor fetches an asynchronous event handler to processes an asynchronous event if the asynchronous event is detected while the result data values are committed to the architectural state of the processor.

摘要翻译： 用于协调处理器中的异常的方法和电路。 处理器为每个指令生成结果数据值和异常数据值，其中异常数据值指定相应指令是否引起异常。 处理器以顺序程序顺序将结果数据值提交给处理器的架构状态，并且如果异常由异常数据值之一指示，则提取异常处理程序来处理异常。 如果在结果数据值提交到处理器的架构状态时检测到异步事件，处理器将获取异步事件处理程序来处理异步事件。

公开(公告)号：US5717882A

公开(公告)日：1998-02-10

申请号：US764643

申请日：1996-12-11

申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth ,  Michael A. Fetterman

发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth ,  Michael A. Fetterman

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836

摘要： A method and apparatus for performing operations with a processor in a computer system. Load operations are performed by use of a dispatch pipeline and a memory execution pipeline. The dispatch pipeline dispatches the load operation for execution by the processor, while the memory execution pipeline controls the execution of the load operation to memory. The present invention reduces the latency involved in executing a load operation by coupling the execution of the two pipelines during execution of the load operation.

摘要翻译： 一种用于使用计算机系统中的处理器执行操作的方法和装置。 通过使用调度管道和存储器执行管线来执行加载操作。 调度管道调度处理器执行的加载操作，而存储器执行流水线控制对存储器的加载操作的执行。 本发明通过在执行加载操作期间耦合两条管线的执行来减少执行加载操作所涉及的延迟。

公开(公告)号：US5664137A

公开(公告)日：1997-09-02

申请号：US525499

申请日：1995-09-07

申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Atig A. Bajwa ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Joel Huang ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Prem Pahlajrai

发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Atig A. Bajwa ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Joel Huang ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Prem Pahlajrai

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3889 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857

摘要： A method and apparatus for performing store operations that includes calculating the address and obtaining the data for the store operation. The address represents the memory location to which the data is to be stored. Once the address is calculated and the data obtained, the store operation is committed to processor state. The store operation may be dispatched to memory to complete the execution of the store operation.

摘要翻译： 一种用于执行存储操作的方法和装置，包括计算地址并获得用于存储操作的数据。 地址表示要存储数据的存储器位置。 一旦计算了地址并获得了数据，存储操作就被提交到处理器状态。 可以将存储操作调度到存储器以完成存储操作的执行。

公开(公告)号：US5627985A

公开(公告)日：1997-05-06

申请号：US177244

申请日：1994-01-04

申请人： Michael A. Fetterman ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  Robert P. Colwell

发明人： Michael A. Fetterman ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  Robert P. Colwell

IPC分类号： G06F9/38 ,  G06F9/34

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A speculative execution out of order processor comprising a reorder circuit containing a plurality of physical registers that buffer speculative execution results for integer and floating-point operations, and a real register circuit containing a plurality of committed state registers that buffer committed execution results for either integer or floating-point operations, depending on the register. The reorder and real register circuits read the speculative and committed source data values for incoming micro-ops, and transfer the speculative and committed source data values over to a micro-op dispatch circuit over a common data path. A retire logic circuit commits the speculative execution results to an architectural state by transferring the speculative execution results from the reorder circuit to the real register circuit.

摘要翻译： 一种推测执行乱序处理器，包括一个包含多个物理寄存器的重排序电路，该多个物理寄存器缓冲整数和浮点运算的推测执行结果，以及一个包含多个提交状态寄存器的实际寄存器电路，该寄存器电路缓冲任一整数的提交执行结果 或浮点运算，具体取决于寄存器。 重排序和实际寄存器电路读取输入微操作的推测和确定的源数据值，并通过公共数据路径将推测和承诺的源数据值传输到微操作调度电路。 退出逻辑电路通过将推测执行结果从重新排序电路传送到实际寄存器电路来将推测执行结果提交到架构状态。

公开(公告)号：US5604878A

公开(公告)日：1997-02-18

申请号：US513679

申请日：1995-08-01

申请人： Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

发明人： Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F13/00

CPC分类号： G06F9/3873 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

摘要： Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units.

摘要翻译： 执行可能参与回写冲突的功能单位的管道延长，以避免冲突。 提供逻辑电路用于比较两个并发执行的执行单元管线的深度，以确定冲突是否会发展。 当看来两个执行单元将尝试同时回写时，将指示具有较短流水线的执行单元向其流水线添加一个阶段，将其结果存储在一个时钟周期的延迟缓冲器中。 冲突解决后，延长给定功能单位管道的指示将被撤销。 多级执行单元被设计为用信号通知保留站来延迟各种指令的发送以避免执行单元之间的冲突。

公开(公告)号：US5584037A

公开(公告)日：1996-12-10

申请号：US571377

申请日：1995-12-13

申请人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

发明人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F5/14 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.

摘要翻译： 分配器为循环缓冲区分配条目。 分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。 除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。 每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。 生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。 响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。 分配器具有用于执行无序调度和推测执行的微处理器的应用。 分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。 分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

公开(公告)号：US5564111A

公开(公告)日：1996-10-08

申请号：US315833

申请日：1994-09-30

申请人： Andrew F. Glew ,  Haitham Akkary ,  Robert P. Colwell ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman

发明人： Andrew F. Glew ,  Haitham Akkary ,  Robert P. Colwell ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman

IPC分类号： G06F9/38 ,  G06F11/00 ,  G06F12/10 ,  G06F11/34

CPC分类号： G06F9/3865 ,  G06F11/0751 ,  G06F12/1027 ,  G06F9/3842 ,  G06F2212/684

摘要： A non-blocking translation lookaside buffer is described for use in a microprocessor capable of processing speculative and out-of-order instructions. Upon the detection of a fault, either during a translation lookaside buffer hit or a page table walk performed in response to a translation lookaside buffer miss, information associated with the faulting instruction is stored within a fault register within the translation lookaside buffer. The stored information includes the linear address of the instruction and information identifying the age of instruction. In addition to storing the information within the fault register, a portion of the information is transmitted to a reordering buffer of the microprocessor for storage therein pending retirement of the faulting instruction. Prior to retirement of the faulting instruction, the translation lookaside buffer continues to process further instructions. Upon retirement of each instruction, the reordering buffer determines whether a fault had been detected for that instruction and, if so, the microprocessor is flushed. Then, a branch is taken into microcode. The microcode accesses the linear address and other information stored within the fault register of the translation lookaside buffer and handles the fault. The system is flushed and the microcode is executed only for faulting instructions which actually retire. As such, faults detected while processing speculative instructions based upon mispredicted branches do not prevent further address translations and do not cause the system to be flushed. Method and apparatus implementations are described herein.

摘要翻译： 描述了用于能够处理推测和乱序指令的微处理器中的非阻塞转换后备缓冲器。 在检测到故障时，无论是在翻译后备缓冲器命中还是响应于翻译后备缓冲器未命中执行的页表行走期间，与故障指令相关联的信息都存储在翻译后备缓冲器内的故障寄存器内。 所存储的信息包括指令的线性地址和识别指令年龄的信息。 除了将信息存储在故障寄存器之外，信息的一部分被发送到微处理器的重排序缓冲器以便存储在故障指令中。 在故障指令退出之前，翻译后备缓冲区继续处理进一步的指令。 在每个指令退出后，重新排序缓冲器确定是否检测到该指令发生故障，如果是，则清除微处理器。 然后，一个分支被带入微码。 微代码访问存储在翻译后备缓冲区的故障寄存器内的线性地址和其他信息，并处理故障。 系统被刷新，微代码仅对实际退出的故障指令执行。 因此，基于错误预测的分支处理推测性指令时检测到的故障不会妨碍进一步的地址转换，并且不会导致系统被刷新。 本文描述了方法和装置实现。

公开(公告)号：US5463745A

公开(公告)日：1995-10-31

申请号：US174074

申请日：1993-12-22

申请人： Rohit A. Vidwans ,  Darrell D. Boggs ,  Michael A. Fetterman ,  Andrew F. Glew

发明人： Rohit A. Vidwans ,  Darrell D. Boggs ,  Michael A. Fetterman ,  Andrew F. Glew

IPC分类号： G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： Instructions are fetched and issued by an instruction fetch and issue circuit with the instructions' sizes in program order. An allocate circuit allocates reservation station entries in a reservation station circuit, and reorder buffer entries in a reorder circuit, for the issued instructions in order, storing the instructions' sizes in the allocated reorder buffer entries. The reservation and dispatch circuit dispatches the issued instructions to the execution circuits for execution when they are ready. The execution circuits store the result data including target addresses of branch instructions into the corresponding reorder buffer entries. During each retirement operation, a retire circuit reads the instruction sizes and the target addresses for a predetermined number of issued instructions from their allocated reorder buffer entries. The retire circuit determines two or more speculative next instruction pointers for each of the issued instructions, factoring into consideration whether the issued instructions are branch instructions or not, and their relative positions to each other. Each of the speculative next instruction pointers indicates what the next instruction pointer for the processor should be for retiring a particular combination of the result data values of the issued instructions under consideration. The retire circuit conditionally updates the next instruction pointer with one of the speculative next instruction pointers, depending on how many, if any, of the instructions can actually retire, and whether any of the actually retiring instructions are branch instructions.

摘要翻译： 指令由指令提取和发布电路以指令的大小以程序顺序取出并发出。 分配电路在保留站电路中分配保留站条目，并且重新排序重新排序电路中的缓冲区条目，以便按顺序发布指令，将指令的大小存储在所分配的重排序缓冲器条目中。 预约和调度电路在准备就绪时将发出的指令发送到执行电路执行。 执行电路将包括分支指令的目标地址的结果数据存储到相应的重排序缓冲器条目中。 在每个退休操作期间，退出电路从其分配的重排序缓冲器条目读取预定数量的已发布指令的指令大小和目标地址。 退出电路为每个发出的指令确定两个或更多个推测下一个指令指针，考虑所发出的指令是否是分支指令，以及它们彼此的相对位置。 每个推测下一个指令指针指示处理器的下一个指令指针应该用于退出所考虑的已发出指令的结果数据值的特定组合。 退出电路有条件地使用推测下一个指令指针之一更新下一个指令指针，这取决于指令实际可以退出多少（如果有的话），以及是否有任何实际退出的指令是分支指令。

公开(公告)号：US5404473A

公开(公告)日：1995-04-04

申请号：US204612

申请日：1994-03-01

申请人： David B. Papworth ,  Michael A. Fetterman ,  Andrew F. Glew ,  Lawrence O. Smith, III ,  Michael M. Hancock ,  Beth Schultz

发明人： David B. Papworth ,  Michael A. Fetterman ,  Andrew F. Glew ,  Lawrence O. Smith, III ,  Michael M. Hancock ,  Beth Schultz

IPC分类号： G06F9/308 ,  G06F9/32 ,  G06F9/38 ,  G06F13/00

CPC分类号： G06F9/30018 ,  G06F9/325 ,  G06F9/3842

摘要： In a pipelined processor, an apparatus for handling string operations. When a string operation is received by the processor, the length of the string as specified by the programmer is stored in a register. Next, an instruction sequencer issues an instruction that computes the register value minus a pre-determined number of iterations to be issued into the pipeline. Following the instruction, the pre-determined number of iterations are issued to the pipeline. When the instruction returns with the calculated number, the instruction sequencer then knows exactly how many iterations should be executed. Any extra iterations that had initially been issued are canceled by the execution unit, and additional iterations are issued as necessary. A loop counter in the instruction sequencer is used to track the number of iterations.

摘要翻译： 在流水线处理器中，用于处理字符串操作的装置。 当处理器接收到字符串操作时，由编程器指定的字符串的长度存储在寄存器中。 接下来，指令定序器发出计算寄存器值减去要发布到流水线中的预定数量的迭代的指令。 按照该指令，将预先确定的迭代次数发布到流水线。 当指令以计算出的数字返回时，指令定序器将准确地知道应该执行多少次迭代。 最初发布的任何额外的迭代将被执行单元取消，并根据需要发出额外的迭代。 指令定序器中的循环计数器用于跟踪迭代次数。

公开(公告)号：US06047369A

公开(公告)日：2000-04-04

申请号：US204521

申请日：1994-02-28

申请人： Robert P. Colwell ,  Andrew F. Glew ,  Atiq A. Bajwa ,  Glenn J. Hinton ,  Michael A. Fetterman

发明人： Robert P. Colwell ,  Andrew F. Glew ,  Atiq A. Bajwa ,  Glenn J. Hinton ,  Michael A. Fetterman

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： A mechanism and method for renaming flags within a register alias table ("RAT") to increase processor parallelism and also providing and using flag masks associated with individual instructions. In order to reduce the amount of data dependencies between instructions that are concurrently processed, the flags used by these instructions are renamed. In general, a RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs, for instance) to eliminate false data dependencies between instructions that reduce overall superscalar processing performance for the microprocessor. The renamed flag registers contain several flag bits and various flag bits may be updated or read by different instructions. Also, static and dynamic flag masks are associated with particular instructions and indicate which flags are capable of being updated by a particular instruction and also indicate which flags are actually updated by the instruction. Static flag masks are used in flag renaming and dynamic flag masks are used at retirement. The invention also discovers cases in which a flag register is required that is a superset of the previously renamed flag register portion.

摘要翻译： 一种用于重命名寄存器别名表（“RAT”）中的标志以增加处理器并行性并且还提供和使用与各个指令相关联的标志掩码的机制和方法。 为了减少并发处理的指令之间的数据依赖性，这些指令使用的标志被重命名。 通常，RAT单元提供寄存器重命名以提供比通常在给定宏架构的逻辑寄存器集（例如Intel架构或PowerPC或Alpha设计）内通常可用的更大的物理寄存器集，以消除指令之间的虚假数据依赖性 这降低了微处理器的整体超标量处理性能。 重命名的标志寄存器包含几个标志位，各种标志位可能被不同的指令更新或读取。 此外，静态和动态标志掩码与特定指令相关联，并且指示哪些标志能够被特定指令更新，并且还指示哪些标志实际上被指令更新。 在标志重命名中使用静态标志掩码，退休时使用动态标志掩码。 本发明还发现需要作为先前重命名的标志寄存器部分的超集的标志寄存器的情况。