公开(公告)号：US5584037A

公开(公告)日：1996-12-10

申请号：US571377

申请日：1995-12-13

申请人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

发明人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F5/14 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.

摘要翻译： 分配器为循环缓冲区分配条目。 分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。 除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。 每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。 生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。 响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。 分配器具有用于执行无序调度和推测执行的微处理器的应用。 分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。 分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

公开(公告)号：US5564111A

公开(公告)日：1996-10-08

申请号：US315833

申请日：1994-09-30

申请人： Andrew F. Glew ,  Haitham Akkary ,  Robert P. Colwell ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman

发明人： Andrew F. Glew ,  Haitham Akkary ,  Robert P. Colwell ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman

IPC分类号： G06F9/38 ,  G06F11/00 ,  G06F12/10 ,  G06F11/34

CPC分类号： G06F9/3865 ,  G06F11/0751 ,  G06F12/1027 ,  G06F9/3842 ,  G06F2212/684

摘要： A non-blocking translation lookaside buffer is described for use in a microprocessor capable of processing speculative and out-of-order instructions. Upon the detection of a fault, either during a translation lookaside buffer hit or a page table walk performed in response to a translation lookaside buffer miss, information associated with the faulting instruction is stored within a fault register within the translation lookaside buffer. The stored information includes the linear address of the instruction and information identifying the age of instruction. In addition to storing the information within the fault register, a portion of the information is transmitted to a reordering buffer of the microprocessor for storage therein pending retirement of the faulting instruction. Prior to retirement of the faulting instruction, the translation lookaside buffer continues to process further instructions. Upon retirement of each instruction, the reordering buffer determines whether a fault had been detected for that instruction and, if so, the microprocessor is flushed. Then, a branch is taken into microcode. The microcode accesses the linear address and other information stored within the fault register of the translation lookaside buffer and handles the fault. The system is flushed and the microcode is executed only for faulting instructions which actually retire. As such, faults detected while processing speculative instructions based upon mispredicted branches do not prevent further address translations and do not cause the system to be flushed. Method and apparatus implementations are described herein.

摘要翻译： 描述了用于能够处理推测和乱序指令的微处理器中的非阻塞转换后备缓冲器。 在检测到故障时，无论是在翻译后备缓冲器命中还是响应于翻译后备缓冲器未命中执行的页表行走期间，与故障指令相关联的信息都存储在翻译后备缓冲器内的故障寄存器内。 所存储的信息包括指令的线性地址和识别指令年龄的信息。 除了将信息存储在故障寄存器之外，信息的一部分被发送到微处理器的重排序缓冲器以便存储在故障指令中。 在故障指令退出之前，翻译后备缓冲区继续处理进一步的指令。 在每个指令退出后，重新排序缓冲器确定是否检测到该指令发生故障，如果是，则清除微处理器。 然后，一个分支被带入微码。 微代码访问存储在翻译后备缓冲区的故障寄存器内的线性地址和其他信息，并处理故障。 系统被刷新，微代码仅对实际退出的故障指令执行。 因此，基于错误预测的分支处理推测性指令时检测到的故障不会妨碍进一步的地址转换，并且不会导致系统被刷新。 本文描述了方法和装置实现。

公开(公告)号：US5987600A

公开(公告)日：1999-11-16

申请号：US851140

申请日：1997-05-05

申请人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

发明人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3865 ,  G06F9/3842 ,  G06F9/3863

摘要： A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to processes the exception if the exception is indicated by one of the exception data values. The processor fetches an asynchronous event handler to processes an asynchronous event if the asynchronous event is detected while the result data values are committed to the architectural state of the processor.

摘要翻译： 用于协调处理器中的异常的方法和电路。 处理器为每个指令生成结果数据值和异常数据值，其中异常数据值指定相应指令是否引起异常。 处理器以顺序程序顺序将结果数据值提交给处理器的架构状态，并且如果异常由异常数据值之一指示，则提取异常处理程序来处理异常。 如果在结果数据值提交到处理器的架构状态时检测到异步事件，处理器将获取异步事件处理程序来处理异步事件。

公开(公告)号：US5627985A

公开(公告)日：1997-05-06

申请号：US177244

申请日：1994-01-04

申请人： Michael A. Fetterman ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  Robert P. Colwell

发明人： Michael A. Fetterman ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  Robert P. Colwell

IPC分类号： G06F9/38 ,  G06F9/34

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A speculative execution out of order processor comprising a reorder circuit containing a plurality of physical registers that buffer speculative execution results for integer and floating-point operations, and a real register circuit containing a plurality of committed state registers that buffer committed execution results for either integer or floating-point operations, depending on the register. The reorder and real register circuits read the speculative and committed source data values for incoming micro-ops, and transfer the speculative and committed source data values over to a micro-op dispatch circuit over a common data path. A retire logic circuit commits the speculative execution results to an architectural state by transferring the speculative execution results from the reorder circuit to the real register circuit.

摘要翻译： 一种推测执行乱序处理器，包括一个包含多个物理寄存器的重排序电路，该多个物理寄存器缓冲整数和浮点运算的推测执行结果，以及一个包含多个提交状态寄存器的实际寄存器电路，该寄存器电路缓冲任一整数的提交执行结果 或浮点运算，具体取决于寄存器。 重排序和实际寄存器电路读取输入微操作的推测和确定的源数据值，并通过公共数据路径将推测和承诺的源数据值传输到微操作调度电路。 退出逻辑电路通过将推测执行结果从重新排序电路传送到实际寄存器电路来将推测执行结果提交到架构状态。

公开(公告)号：US5604878A

公开(公告)日：1997-02-18

申请号：US513679

申请日：1995-08-01

申请人： Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

发明人： Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F13/00

CPC分类号： G06F9/3873 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

摘要： Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units.

摘要翻译： 执行可能参与回写冲突的功能单位的管道延长，以避免冲突。 提供逻辑电路用于比较两个并发执行的执行单元管线的深度，以确定冲突是否会发展。 当看来两个执行单元将尝试同时回写时，将指示具有较短流水线的执行单元向其流水线添加一个阶段，将其结果存储在一个时钟周期的延迟缓冲器中。 冲突解决后，延长给定功能单位管道的指示将被撤销。 多级执行单元被设计为用信号通知保留站来延迟各种指令的发送以避免执行单元之间的冲突。

公开(公告)号：US5826094A

公开(公告)日：1998-10-20

申请号：US676887

申请日：1996-07-08

申请人： Robert P. Colwell ,  David B. Papworth ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton

发明人： Robert P. Colwell ,  David B. Papworth ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3828 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A mechanism for indicating within a register alias table (RAT) that certain data has become architecturally visible so that the RAT contains the most recent location of the certain data. Upon receiving the indication that data associated with a particular register is architecturally visible, if a subsequent operation uses the particular register as a source, the data will be supplied from the architecturally visible buffer instead of from an internal buffer (not architecturally visible). The internal buffer is implemented by a reorder buffer (ROB) which contains information associated with instructions that have not yet retired. The architecturally visible buffer is a retirement register file (RRF) which contains information associated with retired instructions. When an instruction retires, the register alias table is searched for the retiring physical register and will indicate within the register alias table that the data associated with the retiring physical register is located within the RRF only if the register alias table has not already (or concurrently) reassigned a new physical register to the logical register associated with the retiring physical register. If the logical register associated with the retiring physical register as been reassigned by subsequent instructions, then no update of the register alias table is required. Also provided is an embodiment for providing the above features in a system wherein the register ordering of the buffers can be altered via register exchange operations.

摘要翻译： 用于在寄存器别名表（RAT）中指示某些数据已经变得架构可见以使得RAT包含特定数据的最新位置的机制。 在接收到与特定寄存器相关联的数据在架构上可见的指示时，如果后续操作使用特定寄存器作为源，则数据将从架构可见缓冲器而不是内部缓冲器（不是架构可见）提供。 内部缓冲器由重新排序缓冲器（ROB）实现，该缓冲器包含与尚未退役的指令相关联的信息。 架构可见的缓冲区是一个退休寄存器文件（RRF），其中包含与退休指令相关的信息。 当指令退出时，对退出的物理寄存器搜索寄存器别名表，并且在寄存器别名表中指示只有当寄存器别名表尚未（或同时）时，与退出物理寄存器相关联的数据位于RRF内 ）将新的物理寄存器重新分配给与退出的物理寄存器相关联的逻辑寄存器。 如果由后续指令重新分配与退役物理寄存器相关联的逻辑寄存器，则不需要更新寄存器别名表。 还提供了一种用于在系统中提供上述特征的实施例，其中缓冲器的寄存器排序可以经由寄存器交换操作来改变。

公开(公告)号：US5751986A

公开(公告)日：1998-05-12

申请号：US778515

申请日：1997-01-03

申请人： Michael A. Fetterman ,  Glenn J. Hinton ,  David B. Papworth ,  Andrew F. Glew ,  Robert P. Colwell

发明人： Michael A. Fetterman ,  Glenn J. Hinton ,  David B. Papworth ,  Andrew F. Glew ,  Robert P. Colwell

IPC分类号： G06F9/38 ,  G06F15/16

CPC分类号： G06F9/3834

摘要： A computer system including a processor having a inherently weakly-ordered memory model comprising a mechanism for emulating strong-ordering to produce self-consistent ordering on a system-wide basis. The processor snoops the system bus externally to determine if a STORE on the external bus hits a LOAD buffer inside the memory subsystem of the processor. If so, the situation is flagged as one which carries the risk of violating processor ordering rules. When the STORE hits the same LOAD address in the LOAD buffer of the processor's memory subsystem, the speculative state of the processor is erased. This cancels the LOAD operation in all subsequent operations. The processor then begins executing from the aborted LOAD; this time loading the newly updated value.

摘要翻译： 一种计算机系统，包括具有固有弱序存储器模型的处理器，该存储器模型包括用于在全系统的基础上模拟强排序以产生自相容排序的机制。 处理器从外部窥探系统总线，以确定外部总线上的存储空间是否与处理器内存子系统中的LOAD缓冲区相匹配。 如果是这样，这种情况被标记为具有违反处理器订购规则的风险。 当STORE在处理器的存储器子系统的LOAD缓冲器中找到相同的LOAD地址时，处理器的推测状态被清除。 这将在所有后续操作中取消LOAD操作。 然后处理器从中止的LOAD开始执行; 这次加载新更新的值。

公开(公告)号：US5687338A

公开(公告)日：1997-11-11

申请号：US511296

申请日：1995-08-04

申请人： Darrell D. Boggs ,  Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Ashwani K. Gupta ,  Glenn J. Hinton ,  David B. Papworth

发明人： Darrell D. Boggs ,  Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Ashwani K. Gupta ,  Glenn J. Hinton ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3814 ,  G06F12/0897 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3863

摘要： A method and apparatus for instruction refetch in a processor is provided. To ensure that a macro instruction is available for refetching after the processor has handled an event or determined a correct restart address after a branch misprediction, an instruction memory includes an instruction cache for caching macro instructions to be fetched, and a victim cache for caching victims from the instruction cache. To ensure the availability of a macro instruction for refetching, the instruction memory (the instruction cache and victim cache together) always stores a macro instruction that may need to be refetched until the macro instruction is committed to architectural state. A marker micro instruction is inserted into the processor pipeline when an instruction cache line is victimized. The marker specifies an entry in the victim cache occupied by the victimized cache line. When the marker instruction is committed to architectural state, the victim cache entry specified by the marker is deallocated in the victim cache to permit storage of other instruction cache victims.

摘要翻译： 提供了一种用于处理器中的指令重写的方法和装置。 为了确保宏指令在处理器处理事件之后可用于重新获取指令，或者在分支错误预测之后确定正确的重新启动地址，指令存储器包括用于缓存要获取的宏指令的指令高速缓存，以及用于缓存受害者的受害缓存 从指令缓存。 为了确保可用的宏指令进行重写，指令存储器（指令高速缓存和受害器缓存在一起）总是存储可能需要重新引导的宏指令，直到宏指令提交到架构状态。 当指令高速缓存线受害时，标记微指令被插入到处理器流水线中。 标记指定受害缓存行占用的受害缓存中的条目。 当标记指令被提交到架构状态时，标记指定的受害者缓存条目被释放在受害缓存中，以允许存储其他指令缓存受害者。

公开(公告)号：US5564056A

公开(公告)日：1996-10-08

申请号：US333397

申请日：1994-11-02

申请人： Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth ,  Robert P. Colwell

发明人： Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth ,  Robert P. Colwell

IPC分类号： G06F9/38 ,  G06F7/00

CPC分类号： G06F9/384 ,  G06F9/3828 ,  G06F9/3855

摘要： Register identification preservation in a microprocessor implementing register renaming. Multiplexing and control circuitry are implemented for manipulating data sources to be supplied to a microprocessor's functional units. The circuitry will generate zero extending for source data to an execution unit where a data source register specified is shorter than a general register size utilized by the microprocessor. Similarly, the multiplexing and control circuitry will shift bits of data from one location to another upon a source input to a functional unit in accordance with control signals designating such activity.

摘要翻译： 在执行寄存器重命名的微处理器中注册识别保存。 实现多路复用和控制电路用于操纵要提供给微处理器功能单元的数据源。 电路将产生零延伸用于源数据到执行单元，其中指定的数据源寄存器比微处理器利用的通用寄存器大小短。 类似地，根据指定这种活动的控制信号，复用和控制电路将根据源输入到功能单元将数据位从一个位置移位到另一个位置。

公开(公告)号：US5913050A

公开(公告)日：1999-06-15

申请号：US735048

申请日：1996-10-22

申请人： Darrell D. Boggs ,  Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth

发明人： Darrell D. Boggs ,  Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F12/06 ,  G06F9/26

CPC分类号： G06F9/3804 ,  G06F9/30054

摘要： This invention overcomes the address size backward compatibility problem by first subtracting the segment base address from the linear destination address of a branch instruction to generate a virtual destination address. It is assumed that the branch instruction destination address is n bits long with m most significant bits. It is desired to provide backward compatibility in the n-bit processor for branch instruction code written for processors utilizing instruction address fields of size (n-m) bits. After obtaining the virtual address, if any of the m most significant bits are non-zero, then those m bits are set to zero to thereby generate a corrected virtual address. If such a compatibility correction is necessary, then a clear signal is asserted to flush all state of the processor that resulted from instructions being fetched after the branch instruction was fetched. The corrected virtual address is added back to the segment base address to generate a corrected linear address. The next instruction is fetched at the corrected linear address.

摘要翻译： 本发明通过首先从分支指令的线性目的地地址中减去分段基地址来生成虚拟目的地地址来克服地址大小向后兼容性问题。 假设分支指令目标地址是n位长，m个最高有效位。 期望在n比特处理器中为使用大小（n-m）比特的指令地址字段为处理器编写的分支指令代码提供向后兼容性。 在获得虚拟地址之后，如果m个最高有效位中的任何一个非零，则将这些m位设置为零，从而生成校正的虚拟地址。 如果需要这种兼容性校正，则清除信号被断言以清除在分支指令被取出之后被取出的指令导致的处理器的所有状态。 校正的虚拟地址被加回到段基地址以产生校正的线性地址。 下一条指令是在校正的线性地址处获取的。