公开(公告)号：US06928494B1

公开(公告)日：2005-08-09

申请号：US09538386

申请日：2000-03-29

申请人： Andrew M. Volk ,  Michael W. Williams ,  David J. McDonnell

发明人： Andrew M. Volk ,  Michael W. Williams ,  David J. McDonnell

IPC分类号： G11C7/10 ,  G06F3/00

CPC分类号： G11C7/10

摘要： A method and apparatus for communicating commands and/or data between two different time domains. In one embodiment, multiple memory commands are placed into one or more FIFOs in a manner that specifies the delays that must take place between execution of the different commands. Along with the commands, delay information is placed into the FIFOs, specifying the number of clock cycles, or other form of time delay, that must elapse between execution of a command and execution of a subsequent command. This delay information is used to delay the execution of the subsequent command for the specified time period, while minimizing or eliminating any excess delays. Cue information can also be placed into the FIFOs with the commands to specify which commands must wait for other commands before beginning execution. The delay and cue information is determined and created in the time domain that initiates the transfers. The delays and cueing are executed in the other time domain. Although the different commands may be delivered through different FIFOs and can therefore have unpredictable arrival times with respect to each other, the delay and cueing information maintains the proper execution order and timing between the commands. Interactive control logic at the output of each FIFO uses the timing data to maintain execution in the proper order and with the proper inter-command delays.

摘要翻译： 一种用于在两个不同时域之间传送命令和/或数据的方法和装置。 在一个实施例中，多个存储器命令以指定在不同命令的执行之间必须发生的延迟的方式被放置到一个或多个FIFO中。 与命令一起，将延迟信息放入FIFO中，指定执行命令和执行后续命令之间必须经过的时钟周期数量或其他形式的时间延迟。 该延迟信息用于在指定的时间段内延迟后续命令的执行，同时最小化或消除任何多余的延迟。 提示信息也可以放在FIFO中，其命令用于指定哪些命令在开始执行之前必须等待其他命令。 在启动传输的时域中确定和创建延迟和提示信息。 延迟和提示在其他时间域执行。 虽然不同的命令可以通过不同的FIFO传递，并且因此可以相对于彼此具有不可预测的到达时间，但延迟和提示信息保持命令之间的正确的执行顺序和定时。 每个FIFO的输出端的交互控制逻辑使用定时数据来维持正确顺序的执行和适当的指令间延迟。

公开(公告)号：US06915399B1

公开(公告)日：2005-07-05

申请号：US09524942

申请日：2000-03-14

申请人： David J. McDonnell ,  Andrew M. Volk ,  Michael W. Williams

发明人： David J. McDonnell ,  Andrew M. Volk ,  Michael W. Williams

IPC分类号： G06F1/04 ,  G06F12/00 ,  G06F13/00 ,  H04L12/403 ,  H04L12/54

CPC分类号： G06F5/06 ,  G06F13/1689 ,  G06F2205/061

摘要： An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a storage circuit in a second clock domain during each cycle of the first clock domain. Each set of N units is selected by the output circuit to include (1) units of information that have previously loaded into the storage circuit and that will not be output from the storage output from the storage circuit prior to the storage circuit being loaded with a subsequent set of N units of information, and (2) a complement number of units of information that have not previously been loaded into the storage circuit.

摘要翻译： 一种用于在时钟域之间传送信息单元的装置和方法。 在第一时钟域的每个周期期间，将相应的N个信息单元从第一时钟域中的输出电路加载到第二时钟域中的存储电路中。 每一组N个单元由输出电路选择，以包括（1）先前已经加载到存储电路中的信息单元，并且在存储电路被加载之前不会从存储电路的存储输出输出 随后的一组N个信息，以及（2）补充数量的先前未被加载到存储电路中的信息单元。

公开(公告)号：US6128749A

公开(公告)日：2000-10-03

申请号：US186046

申请日：1998-11-03

申请人： David J. McDonnell ,  Andrew M. Volk ,  Michael W. Williams

发明人： David J. McDonnell ,  Andrew M. Volk ,  Michael W. Williams

IPC分类号： G06F1/04 ,  G06F12/00 ,  G06F13/00 ,  H04L12/403 ,  H04L12/54

CPC分类号： G06F5/06 ,  G06F13/1689 ,  G06F2205/061

摘要： An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a storage circuit in a second clock domain during each cycle of the first clock domain. Each set of N units is selected by the output circuit to include (1) units of information that have previously been loaded into the storage circuit and that will not be output from the storage circuit prior to the storage circuit being loaded with a subsequent set of N units of information, and (2) a complement number of units of information that have not previously been loaded into the storage circuit.

摘要翻译： 一种用于在时钟域之间传送信息单元的装置和方法。 在第一时钟域的每个周期期间，将相应的N个信息单元从第一时钟域中的输出电路加载到第二时钟域中的存储电路中。 每一组N个单元由输出电路选择，包括（1）先前已经被加载到存储电路中的信息单元，并且在存储电路装载下一组 N个信息单元，以及（2）尚未加载到存储电路中的补充信息单元。

公开(公告)号：US06604179B2

公开(公告)日：2003-08-05

申请号：US09532428

申请日：2000-03-23

申请人： Andrew M. Volk ,  Michael W. Williams

发明人： Andrew M. Volk ,  Michael W. Williams

IPC分类号： G06F1200

CPC分类号： G06F5/10

摘要： A first-in first-out buffer (FIFO) with multiple outputs. The FIFO has an input for writing data into the FIFO. The FIFO has multiple outputs for reading the data out of the FIFO. Each output is independent from the other outputs, and can be used to read data from a different address at a different time using a different clock signal. In one embodiment, the FIFO is implemented as a storage array with circular pointers to repeatedly loop through the addressable locations. It includes a write pointer to indicate which address represents the input. It includes multiple read pointers to indicate which addresses represent the outputs. Overrun prevention logic is used to assure that the write pointer will not cause new data to be written into any address that has not been read by all outputs, and to assure that data will not be read from any address that has not been written into.

摘要翻译： 具有多个输出的先进先出缓冲器（FIFO）。 FIFO具有用于将数据写入FIFO的输入。 FIFO具有多个输出，用于读取FIFO中的数据。 每个输出独立于其他输出，并且可以用于使用不同的时钟信号在不同的时间从不同的地址读取数据。 在一个实施例中，FIFO被实现为具有循环指针的存储阵列，以重复地循环通过可寻址位置。 它包括一个写指针，指示哪个地址代表输入。 它包括多个读指针，以指示哪些地址表示输出。 超程预防逻辑用于确保写指针不会将新数据写入任何未被所有输出读取的地址，并确保数据不会从未写入的任何地址读取。

公开(公告)号：US6112306A

公开(公告)日：2000-08-29

申请号：US167507

申请日：1998-10-06

申请人： Andrew M. Volk ,  Michael W. Williams

发明人： Andrew M. Volk ,  Michael W. Williams

IPC分类号： G06F1/32 ,  G11C7/10 ,  G11C7/22

CPC分类号： G06F1/3225 ,  G11C7/1039 ,  G11C7/22

摘要： A self-synchronizing method and apparatus for exiting a dynamic random access memory from a low power state is provided. The exit from the low power state is initiated. After the expiration of an exit delay period, a first quiet time is sent on a column-access pin. A second quiet time is sent on a row-access pins to reset the memory. The first quiet time and the second quiet time are not necessarily concurrent.

摘要翻译： 提供了一种用于从低功率状态退出动态随机存取存储器的自同步方法和装置。 启动从低功率状态的退出。 退出延迟时间到期后，在列访问引脚上发送第一个安静时间。 在行访问引脚上发送第二个安静的时间以重置内存。 第一个安静的时间和第二个安静的时间并不一定是并行的。

公开(公告)号：US20150032941A1

公开(公告)日：2015-01-29

申请号：US14128669

申请日：2013-07-25

申请人： Eng Hun Ooi ,  Robert J. Royer, JR. ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

发明人： Eng Hun Ooi ,  Robert J. Royer, JR. ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

摘要： In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

摘要翻译： 在一个实施例中，存储器接口可以发送请求被发送的指示。 该指示可以经由存储器接口和非易失性存储器之间的点对点总线发送到非易失性存储器。 存储器接口可以经由总线将请求发送到非易失性存储器。 请求可以包括可用于标识用于存储或读取数据的位置的地址。 非易失性存储器可以从总线获取请求并处理请求。 在处理请求之后，非易失性存储器可以向存储器接口发送指示非易失性存储器具有发送到存储器接口的响应的指示。 存储器接口可以向总线授予对非易失性存储器的访问。 在被允许访问总线之后，非易失性存储器可以将响应发送到存储器接口。

公开(公告)号：US06618791B1

公开(公告)日：2003-09-09

申请号：US09677138

申请日：2000-09-29

申请人： James M. Dodd ,  Michael W. Williams

发明人： James M. Dodd ,  Michael W. Williams

IPC分类号： G06F1200

CPC分类号： G11C5/143 ,  G06F1/3225 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D50/20

摘要： A memory system and a method for controlling power states of a memory device, or a portion thereof, are provided. The memory system includes memory devices, such as DRAMs, a memory controller, chip select lines, and logic for detecting chip select signals from the chip select lines. Each memory device, or a portion therein, is connected to the memory controller by a chip select line. Each chip select line allows the transmission of a chip select signal to a corresponding memory device, or a corresponding portion of the memory device, to select the corresponding memory device, or a portion thereof, to receive commands. Logic is provided to detect the chip select signal. When the logic detects a chip select signal provided to a corresponding memory device, or a portion thereof, that is in a power state lower than its idle state, the memory device, or a portion thereof, is automatically moved from the lower power state to a higher power state.

摘要翻译： 提供了一种用于控制存储器件或其一部分的电源状态的存储器系统和方法。 存储器系统包括诸如DRAM的存储器件，存储器控制器，芯片选择线以及用于检测来自芯片选择线的芯片选择信号的逻辑。 每个存储器件或其中的部分通过芯片选择线连接到存储器控制器。 每个芯片选择线允许将芯片选择信号传输到对应的存储器件或存储器件的相应部分，以选择相应的存储器件或其一部分来接收命令。 提供逻辑来检测芯片选择信号。 当逻辑检测到提供给处于低于其空闲状态的功率状态的相应存储器件或其一部分的芯片选择信号时，存储器件或其一部分自动从较低功率状态移动到 更高的功率状态。

公开(公告)号：US06400631B1

公开(公告)日：2002-06-04

申请号：US09662728

申请日：2000-09-15

申请人： Michael W. Williams ,  Jim M. Dodd

发明人： Michael W. Williams ,  Jim M. Dodd

IPC分类号： G11C1304

CPC分类号： G11C11/406

摘要： A memory containing a plurality of memory banks and a plurality of sense amplifiers. Also, the memory device contains a multiplexer and logic. The logic receives a refresh request for one of the plurality of memory banks and instructs the multiplexer to select one of the plurality of sense amplifiers in response to the refresh request.

摘要翻译： 一种包含多个存储体和多个读出放大器的存储器。 此外，存储器件包含多路复用器和逻辑。 逻辑接收对多个存储器组中的一个的刷新请求，并且指示多路复用器响应于刷新请求选择多个读出放大器之一。

公开(公告)号：US06226730B1

公开(公告)日：2001-05-01

申请号：US09092426

申请日：1998-06-05

申请人： Robert N. Murdoch ,  Michael W. Williams

发明人： Robert N. Murdoch ,  Michael W. Williams

IPC分类号： G06F1210

CPC分类号： G06F12/0215

摘要： An apparatus and method for accessing a memory. A source address that includes a page address and a page offset is received. The page address requires translation in order to form a first address that can be used to transfer data from a row of memory cells into a sense amplifier array in a memory. The page address is compared to contents of one or more page registers to determine if the data is present in the sense amplifier array as a result of a previous memory access. A second address is asserted to access a portion of the data if the data is determined to be present in the sense amplifier array.

摘要翻译： 一种用于访问存储器的装置和方法。 接收包含页面地址和页面偏移的源地址。 页面地址需要转换以形成可以用于将数据从一行存储器单元传送到存储器中的读出放大器阵列的第一地址。 将页面地址与一个或多个页面寄存器的内容进行比较，以确定数据是否作为先前存储器访问的结果存在于读出放大器阵列中。 如果数据被确定为存在于读出放大器阵列中，则第二地址被断言以访问数据的一部分。

公开(公告)号：US20090316800A1

公开(公告)日：2009-12-24

申请号：US12583920

申请日：2009-08-24

申请人： David J. Zimmerman ,  Michael W. Williams

发明人： David J. Zimmerman ,  Michael W. Williams

IPC分类号： H04B3/00 ,  G06F12/06

CPC分类号： G06F13/28 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4096

摘要： Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

摘要翻译： 实施例通过高速串行链路以比高速串行链路常规操作更慢的速度提供对存储器的访问。 实施例可以包括具有耦合到协议识别电路的差分接收器的存储器设备，具有与差分接收器的第一输入端耦合的第一接收器的低速接收电路和与差分接收器的第二输入端耦合的第二接收器 其中低速接收电路与协议识别电路耦合，允许第一和第二接收机以与差分接收机不同的频率访问协议识别块。