公开(公告)号：US20100144105A1

公开(公告)日：2010-06-10

申请号：US12330296

申请日：2008-12-08

申请人： Andrew M. Waite ,  Andy C. Wei

发明人： Andrew M. Waite ,  Andy C. Wei

IPC分类号： H01L21/8238 ,  H01L21/8232

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are implanted into the polycrystalline silicon gate electrode layer to form a P-type implanted region and a first polycrystalline silicon gate electrode is formed overlying the P-well region. Recesses are etched into the P-well region using the first polycrystalline silicon gate electrode as an etch mask. The step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide. A tensile stress-inducing material is formed within the recesses.

摘要翻译： 提供制造应力MOS器件的方法。 在一个实施例中，该方法包括提供具有P阱区域并沉积覆盖P阱区域的多晶硅栅电极层的硅衬底。 将P型掺杂剂离子注入到多晶硅栅电极层中以形成P型注入区，并且在P阱区上形成第一多晶硅栅电极。 使用第一多晶硅栅电极作为蚀刻掩模将凹陷蚀刻到P阱区中。 通过将硅衬底暴露于四甲基氢氧化铵来进行蚀刻步骤。 在凹部内形成拉伸应力诱发材料。

公开(公告)号：US07977180B2

公开(公告)日：2011-07-12

申请号：US12330296

申请日：2008-12-08

申请人： Andrew M. Waite ,  Andy C. Wei

发明人： Andrew M. Waite ,  Andy C. Wei

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are implanted into the polycrystalline silicon gate electrode layer to form a P-type implanted region and a first polycrystalline silicon gate electrode is formed overlying the P-well region. Recesses are etched into the P-well region using the first polycrystalline silicon gate electrode as an etch mask. The step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide. A tensile stress-inducing material is formed within the recesses.

摘要翻译： 提供制造应力MOS器件的方法。 在一个实施例中，该方法包括提供具有P阱区域并沉积覆盖P阱区域的多晶硅栅电极层的硅衬底。 将P型掺杂剂离子注入到多晶硅栅电极层中以形成P型注入区，并且在P阱区上形成第一多晶硅栅电极。 使用第一多晶硅栅电极作为蚀刻掩模将凹陷蚀刻到P阱区中。 通过将硅衬底暴露于四甲基氢氧化铵来进行蚀刻步骤。 在凹部内形成拉伸应力诱发材料。

公开(公告)号：US20140004692A1

公开(公告)日：2014-01-02

申请号：US13539727

申请日：2012-07-02

申请人： Andy C. Wei ,  Akshey Sehgal ,  Bamidele S. Allimi

发明人： Andy C. Wei ,  Akshey Sehgal ,  Bamidele S. Allimi

IPC分类号： H01L21/283

CPC分类号： H01L21/823821 ,  H01L29/66545

摘要： A method for fabricating a multiple-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure and etching the first workfunction material layer so as to completely remove the first workfunction material layer from all but a first trench of the plurality of trenches. Further, the method includes depositing a second workfunction material in a layer in the plurality of trenches and etching the second workfunction material layer so as to completely remove the second workfunction material layer from all but a second trench of the plurality of trenches. Still further, the method includes depositing a third workfunction material in a layer in the plurality of trenches.

摘要翻译： 一种用于制造多功能FinFET结构的方法，包括：在FinFET结构的多个沟槽中的层中沉积第一功函数材料，并蚀刻第一功函数材料层，以从第一功函数材料层中除去第一功函数材料层 多个沟槽的沟槽。 此外，所述方法包括在所述多个沟槽中的层中沉积第二功函数材料并蚀刻所述第二功函数材料层，以便从所述多个沟槽中的所有除第二沟槽以外的全部除去所述第二功函数材料层。 此外，该方法包括在多个沟槽中的层中沉积第三功函数材料。

公开(公告)号：US07544999B2

公开(公告)日：2009-06-09

申请号：US11072661

申请日：2005-03-04

申请人： Andy C. Wei ,  Derick J. Wristers ,  Mark B. Fuselier

发明人： Andy C. Wei ,  Derick J. Wristers ,  Mark B. Fuselier

IPC分类号： H01L27/12

CPC分类号： H01L29/66772 ,  H01L29/78603

摘要： In one illustrative embodiment, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric regions in the bulk substrate after the gate electrode is formed, the dielectric regions being self-aligned with respect to the gate electrode, the dielectric regions having a dielectric constant that is less than a dielectric constant of the bulk substrate. In further embodiments, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, performing at least one oxygen implant process after the gate electrode and the protective layer are formed to introduce oxygen atoms into the bulk substrate to thereby form a plurality of oxygen-doped regions in the bulk substrate, and performing at least one anneal process to convert the oxygen-doped regions to dielectric regions comprised of silicon dioxide in the bulk substrate. In one illustrative embodiment, the device comprises a gate electrode formed above an SOI structure comprised of a bulk substrate, a buried insulation layer, and an active layer, and a plurality of dielectric regions comprised of silicon dioxide formed in the bulk substrate, the dielectric regions being self-aligned with respect to the gate electrode.

摘要翻译： 在一个说明性实施例中，该方法包括在由大量衬底，掩埋绝缘层和有源层组成的SOI衬底之上形成栅电极，该栅电极具有形成在其上的保护层，并且在该衬底中形成多个电介质区域 在栅电极形成之后，电介质区域相对于栅电极自对准，介质区域的介电常数小于体基板的介电常数。 在另外的实施例中，该方法包括在由大量衬底，掩埋绝缘层和有源层组成的SOI衬底之上形成栅电极，栅极具有形成在其上的保护层，在栅极之后执行至少一个氧注入工艺 形成电极和保护层，以将氧原子引入本体衬底中，从而在本体衬底中形成多个氧掺杂区域，并且执行至少一个退火工艺以将氧掺杂区域转换成由硅构成的电介质区域 散装衬底中的二氧化物。 在一个说明性实施例中，该器件包括形成在SOI结构之上的栅电极，该SOI结构包括体衬底，掩埋绝缘层和有源层，以及由形成在本体衬底中的二氧化硅构成的多个电介质区域， 区域相对于栅电极自对准。

公开(公告)号：US07129142B2

公开(公告)日：2006-10-31

申请号：US10167184

申请日：2002-06-11

申请人： Derick J. Wristers ,  Andy C. Wei ,  Mark B. Fuselier

发明人： Derick J. Wristers ,  Andy C. Wei ,  Mark B. Fuselier

IPC分类号： H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors above the SOI substrate in an area above the doped region and applying a voltage to the doped region to vary a threshold voltage of at least one of the plurality of transistors. In another illustrative embodiment, the method comprises providing a consumer product comprised of at least one integrated circuit product, the integrated circuit product being comprised of a plurality of transistors formed in an active layer of an SOI substrate above a doped region formed in a bulk substrate of the SOI substrate, the doped region being formed under the active layer, sensing an activity level of the integrated circuit product and applying a voltage of a magnitude and a polarity to the doped region, the magnitude and polarity of the applied voltage being determined based upon the sensed activity level of the integrated circuit product.

公开(公告)号：US08673759B2

公开(公告)日：2014-03-18

申请号：US13398991

申请日：2012-02-17

申请人： Chris M. Prindle ,  Klaus Hempel ,  Andy C. Wei

发明人： Chris M. Prindle ,  Klaus Hempel ,  Andy C. Wei

IPC分类号： H01L21/28

CPC分类号： H01L21/28114 ,  H01L21/32131 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/66545

摘要： Semiconductor devices are formed with a gate last, high-K/metal gate process with complete removal of the polysilicon dummy gate and with a gap having a low aspect ratio for the metal fill. Embodiments include forming a dummy gate electrode on a substrate, the dummy gate electrode having a nitride cap, forming spacers adjacent opposite sides of the dummy gate electrode forming a gate trench therebetween, dry etching the nitride cap, tapering the gate trench top corners; performing a selective dry etch on a portion of the dummy gate electrode, and wet etching the remainder of the dummy gate electrode.

摘要翻译： 半导体器件形成有最后的高K /金属栅极工艺，完全去除多晶硅虚拟栅极并且具有用于金属填充物的低纵横比的间隙。 实施例包括在基板上形成虚拟栅电极，虚拟栅电极具有氮化物盖，在虚拟栅电极的相对侧上形成隔板，在其间形成栅极沟槽，干蚀刻氮化物盖，使栅极沟槽顶角逐渐变细; 在虚拟栅电极的一部分上进行选择性干蚀刻，并湿法蚀刻伪栅电极的其余部分。

公开(公告)号：US20140038402A1

公开(公告)日：2014-02-06

申请号：US13563202

申请日：2012-07-31

申请人： Andy C. Wei ,  Bin Yang ,  Francis M. Tambwe

发明人： Andy C. Wei ,  Bin Yang ,  Francis M. Tambwe

IPC分类号： H01L21/336 ,  H01L21/311

CPC分类号： H01L27/11 ,  H01L21/823821 ,  H01L29/7843

摘要： A method for fabricating a dual-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the FinFET structure. The method further includes depositing a second workfunction material in a layer in a plurality of trenches of the portion and depositing a stress material layer over the second workfunction material layer.

摘要翻译： 一种用于制造双功函数FinFET结构的方法，包括在FinFET结构的多个沟槽中的层中沉积第一功函数材料，在第一功函数材料层上沉积低电阻材料层，以及蚀刻低电阻材料 层和来自FinFET结构的一部分的第一功函数材料层。 该方法还包括在该部分的多个沟槽中的层中沉积第二功函数材料，并在第二功函数材料层上沉积应力材料层。

公开(公告)号：US20130309838A1

公开(公告)日：2013-11-21

申请号：US13474443

申请日：2012-05-17

申请人： Andy C. Wei ,  Francis C. Tambwe ,  Frank Scott Johnson

发明人： Andy C. Wei ,  Francis C. Tambwe ,  Frank Scott Johnson

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/6681

摘要： Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.

摘要翻译： 提供了用于在体半导体衬底上制造FinFET集成电路的方法。 根据一个实施例，形成覆盖半导体衬底的限定多个翅片的规则阵列的位置的图案化硬掩模。 使用切割掩模去除图案化硬掩模的部分以形成修改的硬掩模。 使用改进的硬掩模作为蚀刻掩模蚀刻衬底，以形成从衬底向上延伸并由沟槽分离的多个鳍。 至少部分地去除多个翅片中的选定的翅片以形成隔离区域，并且沉积绝缘材料以填充沟槽并且覆盖多个翅片中的至少部分移除的选定翼片。

公开(公告)号：US07432136B2

公开(公告)日：2008-10-07

申请号：US10140441

申请日：2002-05-06

申请人： Mark B. Fuselier ,  Derick J. Wristers ,  Andy C. Wei

发明人： Mark B. Fuselier ,  Derick J. Wristers ,  Andy C. Wei

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/78648 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78609

摘要： In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, the active layer being doped with a first type of dopant material, the bulk substrate having an inner well formed therein adjacent a surface of the bulk substrate and under the active layer, the inner well being doped with the first type of dopant material, forming a transistor above the SOI substrate in an area above the inner well and applying a voltage to the inner well to vary a threshold voltage of the transistor. In some embodiments, the method further comprises forming an NMOS transistor, wherein the active layer and the inner well are doped with a P-type dopant material. In other embodiments, the method further comprises forming a PMOS transistor, wherein the active layer and the inner well are doped with an N-type dopant material. In another illustrative embodiment, the method comprises providing a consumer product comprised of at least one integrated circuit product, the integrated circuit product being comprised of at least one transistor formed in an active layer of an SOI substrate, the SOI substrate further comprising an inner well formed adjacent a surface of a bulk substrate of the SOI substrate, the inner well being formed under the active layer, the active layer and the inner well being doped with a first type of dopant material, sensing an activity level of the integrated circuit product and applying a voltage of a magnitude and a polarity to the inner well of at least one transistor, the magnitude and polarity of the applied voltage being determined based upon the sensed activity level of the integrated circuit product.

摘要翻译： 在一个说明性实施例中，该方法包括提供由有源层，掩埋绝缘层和体基板构成的SOI衬底，所述有源层掺杂有第一类型的掺杂剂材料，所述主体衬底具有形成在其中的内阱 所述体衬底的表面并且在所述有源层下方，所述内阱掺杂有所述第一类型的掺杂剂材料，在所述内阱上方的区域中在所述SOI衬底上方形成晶体管，并向所述内阱施加电压以改变 晶体管的阈值电压。 在一些实施例中，该方法还包括形成NMOS晶体管，其中有源层和内阱掺杂有P型掺杂剂材料。 在其他实施例中，该方法还包括形成PMOS晶体管，其中有源层和内阱掺杂有N型掺杂剂材料。 在另一说明性实施例中，该方法包括提供由至少一个集成电路产品组成的消费产品，所述集成电路产品由形成在SOI衬底的有源层中的至少一个晶体管组成，所述SOI衬底还包括内部阱 形成在所述SOI衬底的本体衬底的表面附近，所述内阱形成在所述有源层下方，所述有源层和所述内阱掺杂有第一类型的掺杂剂材料，感测所述集成电路产品的活动水平，以及 对至少一个晶体管的内部阱施加大小和极性的电压，所施加的电压的大小和极性基于感测到的集成电路产品的活动水平来确定。

公开(公告)号：US08975141B2

公开(公告)日：2015-03-10

申请号：US13563202

申请日：2012-07-31

申请人： Andy C. Wei ,  Bin Yang ,  Francis M. Tambwe

发明人： Andy C. Wei ,  Bin Yang ,  Francis M. Tambwe

IPC分类号： H01L21/336

CPC分类号： H01L27/11 ,  H01L21/823821 ,  H01L29/7843

摘要： A method for fabricating a dual-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the FinFET structure. The method further includes depositing a second workfunction material in a layer in a plurality of trenches of the portion and depositing a stress material layer over the second workfunction material layer.

摘要翻译： 一种用于制造双功函数FinFET结构的方法，包括在FinFET结构的多个沟槽中的层中沉积第一功函数材料，在第一功函数材料层上沉积低电阻材料层，以及蚀刻低电阻材料 层和来自FinFET结构的一部分的第一功函数材料层。 该方法还包括在该部分的多个沟槽中的层中沉积第二功函数材料，并在第二功函数材料层上沉积应力材料层。