公开(公告)号：US07157374B1

公开(公告)日：2007-01-02

申请号：US10876544

申请日：2004-06-28

申请人： Andrew M. Waite ,  Huicai Zhong

发明人： Andrew M. Waite ,  Huicai Zhong

IPC分类号： H01L21/302

CPC分类号： H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  Y10S257/90

摘要： A method of removing the cap from a gate of an embedded SiGe semiconductor device includes the formation of the embedded SiGe semiconductor device with the cap consisting of a cap material on top of the gate, first sidewall spacers on side surfaces of the gate, and embedded SiGe in source and drain regions. Second sidewall spacers are formed on the first sidewall spacers, these second sidewall spacers consisting of a material different from the cap material. The cap is stripped from the top of the gate with an etchant that selectively etches the cap material and not the second sidewall spacer material.

摘要翻译： 从嵌入式SiGe半导体器件的栅极去除帽子的方法包括形成嵌入式SiGe半导体器件，其中盖子由栅极顶部的帽材料构成，栅极侧表面上的第一侧壁间隔物和嵌入的 源区和漏区的SiGe。 第二侧壁间隔件形成在第一侧壁间隔件上，这些第二侧壁间隔件由不同于盖材料的材料组成。 使用选择性蚀刻帽材料而不是第二侧壁间隔物材料的蚀刻剂从盖的顶部剥离盖。

公开(公告)号：US07977180B2

公开(公告)日：2011-07-12

申请号：US12330296

申请日：2008-12-08

申请人： Andrew M. Waite ,  Andy C. Wei

发明人： Andrew M. Waite ,  Andy C. Wei

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are implanted into the polycrystalline silicon gate electrode layer to form a P-type implanted region and a first polycrystalline silicon gate electrode is formed overlying the P-well region. Recesses are etched into the P-well region using the first polycrystalline silicon gate electrode as an etch mask. The step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide. A tensile stress-inducing material is formed within the recesses.

摘要翻译： 提供制造应力MOS器件的方法。 在一个实施例中，该方法包括提供具有P阱区域并沉积覆盖P阱区域的多晶硅栅电极层的硅衬底。 将P型掺杂剂离子注入到多晶硅栅电极层中以形成P型注入区，并且在P阱区上形成第一多晶硅栅电极。 使用第一多晶硅栅电极作为蚀刻掩模将凹陷蚀刻到P阱区中。 通过将硅衬底暴露于四甲基氢氧化铵来进行蚀刻步骤。 在凹部内形成拉伸应力诱发材料。

公开(公告)号：US06972478B1

公开(公告)日：2005-12-06

申请号：US11075774

申请日：2005-03-07

申请人： Andrew M. Waite ,  Scott Luning

发明人： Andrew M. Waite ,  Scott Luning

IPC分类号： H01L21/20 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/78

CPC分类号： H01L29/045 ,  H01L21/2007 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7833

摘要： An integrated circuit and methods for its manufacture are provided. The integrated circuit comprises a bulk silicon substrate having a first region of crystalline orientation and a second region of crystalline orientation. A layer of silicon on insulator overlies a portion of the bulk silicon substrate. At least one field effect transistor is formed in the layer of silicon on insulator, at least one P-channel field effect transistor is formed in the second region of crystalline orientation, and at least one N-channel field effect transistor is formed in the first region of crystalline orientation.

摘要翻译： 提供集成电路及其制造方法。 集成电路包括具有<100>晶体取向的第一区域和<110>晶体取向的第二区域的体硅衬底。 绝缘体上的一层覆盖在体硅衬底的一部分上。 在绝缘体上的硅层中形成至少一个场效应晶体管，在<110>晶取向的第二区域中形成至少一个P沟道场效应晶体管，并形成至少一个N沟道场效应晶体管 在<100>晶体取向的第一区域。

公开(公告)号：US20100144105A1

公开(公告)日：2010-06-10

申请号：US12330296

申请日：2008-12-08

申请人： Andrew M. Waite ,  Andy C. Wei

发明人： Andrew M. Waite ,  Andy C. Wei

IPC分类号： H01L21/8238 ,  H01L21/8232

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are implanted into the polycrystalline silicon gate electrode layer to form a P-type implanted region and a first polycrystalline silicon gate electrode is formed overlying the P-well region. Recesses are etched into the P-well region using the first polycrystalline silicon gate electrode as an etch mask. The step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide. A tensile stress-inducing material is formed within the recesses.

摘要翻译： 提供制造应力MOS器件的方法。 在一个实施例中，该方法包括提供具有P阱区域并沉积覆盖P阱区域的多晶硅栅电极层的硅衬底。 将P型掺杂剂离子注入到多晶硅栅电极层中以形成P型注入区，并且在P阱区上形成第一多晶硅栅电极。 使用第一多晶硅栅电极作为蚀刻掩模将凹陷蚀刻到P阱区中。 通过将硅衬底暴露于四甲基氢氧化铵来进行蚀刻步骤。 在凹部内形成拉伸应力诱发材料。

公开(公告)号：US07521380B2

公开(公告)日：2009-04-21

申请号：US11738828

申请日：2007-04-23

申请人： Andrew M. Waite ,  Scott Luning ,  Frank (Bin) Yang

发明人： Andrew M. Waite ,  Scott Luning ,  Frank (Bin) Yang

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

摘要： A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart by a second distance greater than the first distance. A first stress liner layer is deposited overlying the NPTs, the WPTs and the semiconductor layer, an etch stop layer is deposited overlying the first stress liner layer, and a second stress liner layer is deposited overlying the etch stop layer. A portion of the second stress liner layer which overlies the WPTs is covered, and an exposed portion of the second stress liner layer which overlies the NPTs is removed to expose an exposed portion of the etch stop layer. The exposed portion of the etch stop layer which overlies the NPTs is removed.

摘要翻译： 提供了一种在半导体衬底上制造半导体器件的方法。 在半导体衬底上形成多个窄栅极间距晶体管（NPT）和宽栅极间距晶体管（WPT）。 NPT间隔开第一距离，并且WPT间隔开大于第一距离的第二距离。 沉积覆盖在NPT，WPT和半导体层上的第一应力衬垫层，沉积覆盖在第一应力衬垫层上的蚀刻停止层，并且沉积覆盖在蚀刻停止层上的第二应力衬垫层。 覆盖在WPT上的第二应力衬垫层的一部分被覆盖，并且去除覆盖在NPT上的第二应力衬垫层的暴露部分以露出蚀刻停止层的暴露部分。 去除覆盖在NPT上的蚀刻停止层的暴露部分。

公开(公告)号：US07179745B1

公开(公告)日：2007-02-20

申请号：US10860100

申请日：2004-06-04

申请人： Andrew M. Waite ,  Jon D. Cheek ,  David Brown

发明人： Andrew M. Waite ,  Jon D. Cheek ,  David Brown

IPC分类号： H01L21/311

CPC分类号： H01L29/7843 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66772

摘要： A method for offsetting silicide on a semiconductor device having a polysilicon gate electrode, source and drain regions in a substrate, and source and drain extensions in the substrate, employs a titanium nitride sidewall spacer on the sidewalls of the polysilicon gate electrode. The titanium nitride sidewall spacer prevents silicide growth on top of the source and drain extensions during a salicidation process. The titanium nitride sidewall spacers are then removed by an etching process that does not etch the silicide regions formed in the source and drain regions and the polysilicon gate electrode. Following removal of the titanium nitride sidewall spacers, a low k interlevel dielectric layer or a stress liner may be deposited on top of the devices to enhance device performance.

摘要翻译： 一种用于在具有多晶硅栅电极，衬底中的源极和漏极区域以及衬底中的源极和漏极延伸部分的半导体器件上偏移硅化物的方法，在多晶硅栅电极的侧壁上采用氮化钛侧壁间隔物。 氮化钛侧壁间隔物防止了在氧化过程中在源极和漏极延伸部分顶部的硅化物生长。 然后通过蚀刻工艺去除氮化钛侧壁间隔物，该蚀刻工艺不蚀刻在源极和漏极区域以及多晶硅栅极电极中形成的硅化物区域。 在移除氮化钛侧壁间隔物之后，可以将低k层间介电层或应力衬垫沉积在器件的顶部以增强器件性能。

公开(公告)号：US07829401B2

公开(公告)日：2010-11-09

申请号：US12121387

申请日：2008-05-15

申请人： Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

发明人： Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

摘要： A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

摘要翻译： 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

公开(公告)号：US07504301B2

公开(公告)日：2009-03-17

申请号：US11536126

申请日：2006-09-28

申请人： Andrew M. Waite ,  Scott Luning

发明人： Andrew M. Waite ,  Scott Luning

IPC分类号： H01L21/00

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

摘要： A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

摘要翻译： 提供了一种应力场效应晶体管及其制造方法。 场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。 栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。 具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。 具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

公开(公告)号：US07224007B1

公开(公告)日：2007-05-29

申请号：US10873240

申请日：2004-06-23

申请人： James Pan ,  Andrew M. Waite

发明人： James Pan ,  Andrew M. Waite

IPC分类号： H01L29/768

CPC分类号： H01L21/26586 ,  H01L21/2807 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A multiple channel transistor provides a transistor with an improved drive current and speed by using tunable hot carrier effects. A thin gate oxide has a carrier confinement layer formed on top thereof. Holes produced by hot carrier effects are retained by the carrier confinement layer directly above the gate oxide layer. The holes switch on the bottom transistor of the multi-channel transistor, thereby increasing the drive current.

摘要翻译： 多通道晶体管通过使用可调热载流子效应为晶体管提供了改进的驱动电流和速度。 薄栅氧化物在其顶部形成有载流子限制层。 由热载体效应产生的孔由栅极氧化物层正上方的载流子限制层保留。 空穴打开多通道晶体管的底部晶体管，从而增加驱动电流。

公开(公告)号：US07183169B1

公开(公告)日：2007-02-27

申请号：US11072312

申请日：2005-03-07

申请人： Andrew M. Waite ,  Scott Luning ,  Philip A. Fisher

发明人： Andrew M. Waite ,  Scott Luning ,  Philip A. Fisher

IPC分类号： H01L21/336

CPC分类号： H01L29/78621 ,  H01L29/665 ,  H01L29/66628

摘要： A method and arrangement for reducing the series resistance of the source and drain in a MOSFET device provides for epitaxially grown regions on top of the source and drain extensions to cover portions of the top surfaces of the silicide regions formed on the substrate. The epitaxial material provides an extra flow path for current to flow through to the silicide from the extension, as well as increasing the surface area between the source/drain and the silicide to reduce the contact resistance between the source/drain and the silicide.

摘要翻译： 用于降低MOSFET器件中的源极和漏极的串联电阻的方法和装置提供了在源极和漏极延伸部的顶部上的外延生长区域，以覆盖形成在衬底上的硅化物区域的顶表面的部分。 外延材料提供了一个额外的流动路径，用于电流从延伸部分流到硅化物，以及增加源极/漏极和硅化物之间的表面积，以减少源极/漏极和硅化物之间的接触电阻。