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公开(公告)号：US20140173297A1
公开(公告)日：2014-06-19
申请号：US13716712
申请日：2012-12-17
申请人： Ankush Varma , Krishnakanth V. Sistla , Ian M. Steiner , Vivek Garg , Chris Poirier , Martin T. Rowland
发明人： Ankush Varma , Krishnakanth V. Sistla , Ian M. Steiner , Vivek Garg , Chris Poirier , Martin T. Rowland
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/32 , G06F1/3203 , G06F1/329 , G06F9/5044 , G06F9/505 , G06F13/00 , G06F15/17325 , G06T1/20 , Y02D10/126
摘要： In an embodiment, a processor includes a core to execute instructions, uncore logic coupled to the core, and a power controller to control a power consumption level. The power controller is configured to determine an activity level of the processor and responsive to this level, to generate a request for communication to a second processor coupled to the processor to request frequency coordination between the processors. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括执行指令的核心，耦合到核心的非逻辑逻辑以及用于控制功耗水平的功率控制器。 功率控制器被配置为确定处理器的活动级别并响应于该级别，以产生与耦合到处理器的第二处理器通信以请求处理器之间的频率协调的请求。 描述和要求保护其他实施例。
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2.发明申请METHOD AND APPARATUS FOR SETTING AN I/O BANDWIDTH-BASED PROCESSOR FREQUENCY FLOOR 有权用于设置基于I / O带宽处理器频率地板的方法和装置公开(公告)号：US20140129858A1
公开(公告)日：2014-05-08
申请号：US13992706
申请日：2011-12-21
申请人： Ankush Varma , Ian M. Steiner , Krishnakanth V. Sistla , Matthew M. Bace , Vivek Garg , Martin T. Rowland , Jeffrey S. Wilder
发明人： Ankush Varma , Ian M. Steiner , Krishnakanth V. Sistla , Matthew M. Bace , Vivek Garg , Martin T. Rowland , Jeffrey S. Wilder
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F13/382
摘要： An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. ThePCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.
摘要翻译： 一种用于管理计算机处理器的频率的装置和方法。 该装置包括用于管理计算机处理器中的电力的功率控制单元（PCU）。 PCU包括数据采集模块，用于从计算机处理器中的多个通信端口获得交易速率数据，以及耦合到数据收集模块的频率控制逻辑模块，频率控制逻辑来计算多个 通信端口来处理流量而没有显着增加的延迟，并且覆盖处理器互连频率以满足计算的最小处理器互连频率。
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公开(公告)号：US09977482B2
公开(公告)日：2018-05-22
申请号：US13992706
申请日：2011-12-21
申请人： Ankush Varma , Ian M. Steiner , Krishnakanth V. Sistla , Matthew M. Bace , Vivek Garg , Martin T. Rowland , Jeffrey S. Wilder
发明人： Ankush Varma , Ian M. Steiner , Krishnakanth V. Sistla , Matthew M. Bace , Vivek Garg , Martin T. Rowland , Jeffrey S. Wilder
CPC分类号： G06F1/324 , G06F13/382
摘要： An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The PCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.
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公开(公告)号：US09158351B2
公开(公告)日：2015-10-13
申请号：US13976687
申请日：2012-03-29
申请人： Ankush Varma , Krishnakanth V. Sistla , Cesar A. Quiroz , Vivek Garg , Martin T. Rowland , Inder M. Sodhi , James S. Burns
发明人： Ankush Varma , Krishnakanth V. Sistla , Cesar A. Quiroz , Vivek Garg , Martin T. Rowland , Inder M. Sodhi , James S. Burns
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/324 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/14 , Y02D10/172
摘要： A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.
摘要翻译： 一种用于在平台中的模块之间动态功率限制共享的方法和装置。 在本发明的一个实施例中，平台包括处理器和存储器模块。 通过扩展功率域以包括处理器和存储器模块，能够在处理器和存储器模块之间动态共享平台的功率预算。 对于低带宽工作负载，功率预算的动态共享为处理器通过使用存储器电源中的余量增加频率提供了重要机会，反之亦然。 这在本发明的一个实施例中能够实现相同的总平台功率预算的更高峰值性能。
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公开(公告)号：US20130332753A1
公开(公告)日：2013-12-12
申请号：US13976687
申请日：2012-03-29
申请人： Ankush Varma , Krishnakanth V. Sistla , Cesar A. Quiroz , Vivek Garg , Martin T. Rowland , Inder M. Sodhi , James S. Burns
发明人： Ankush Varma , Krishnakanth V. Sistla , Cesar A. Quiroz , Vivek Garg , Martin T. Rowland , Inder M. Sodhi , James S. Burns
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/324 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/14 , Y02D10/172
摘要： A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.
摘要翻译： 一种用于在平台中的模块之间动态功率限制共享的方法和装置。 在本发明的一个实施例中，平台包括处理器和存储器模块。 通过扩展功率域以包括处理器和存储器模块，能够在处理器和存储器模块之间动态共享平台的功率预算。 对于低带宽工作负载，功率预算的动态共享为处理器通过使用存储器电源中的余量增加频率提供了重要机会，反之亦然。 这在本发明的一个实施例中能够实现相同的总平台功率预算的更高峰值性能。
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公开(公告)号：US09547027B2
公开(公告)日：2017-01-17
申请号：US13996266
申请日：2012-03-30
IPC分类号： G06F1/00 , G01R21/133 , G06F1/32 , G06F1/26
CPC分类号： G01R21/133 , G06F1/26 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有多个核以独立执行指令的处理器，第一传感器至少部分地基于在核上发生的事件来测量处理器的第一功率消耗水平，以及混合逻辑， 第一功率消耗水平和第二功耗水平。 描述和要求保护其他实施例。
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公开(公告)号：US20140195828A1
公开(公告)日：2014-07-10
申请号：US13996266
申请日：2012-03-30
IPC分类号： G01R21/133 , G06F1/32
CPC分类号： G01R21/133 , G06F1/26 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有多个核以独立执行指令的处理器，第一传感器至少部分地基于在核上发生的事件来测量处理器的第一功率消耗水平，以及混合逻辑， 第一功率消耗水平和第二功耗水平。 描述和要求保护其他实施例。
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8.发明授权Dynamically modifying a power/performance tradeoff based on processor utilization 有权基于处理器利用率动态修改功率/性能折衷公开(公告)号：US09372524B2
公开(公告)日：2016-06-21
申请号：US13326605
申请日：2011-12-15
申请人： Krishnakanth V. Sistla , Mark Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Daniel Borkowski , Vivek Garg , Cagdas Akturan , Avinash N. Ananthakrishnan
发明人： Krishnakanth V. Sistla , Mark Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Daniel Borkowski , Vivek Garg , Cagdas Akturan , Avinash N. Ananthakrishnan
CPC分类号： G06F9/5094 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有功率控制器的多核处理器，所述功率控制器具有在处理器的利用率超过阈值水平时将功率管理策略从功率偏置策略动态切换到性能偏差策略的逻辑。 因此，在低利用率下，可以实现降低的功率消耗，而在更高的利用率下，可以实现更高的性能。 描述和要求保护其他实施例。
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9.发明申请Dynamically Modifying A Power/Performance Tradeoff Based On Processor Utilization 有权基于处理器利用动态修改电源/性能权衡公开(公告)号：US20120144217A1
公开(公告)日：2012-06-07
申请号：US13326605
申请日：2011-12-15
申请人： Krishnakanth V. Sistla , Mark Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Daniel Borkowski , Vivek Garg , Cagdas Akturan , Avinash N. Ananthakrishnan
发明人： Krishnakanth V. Sistla , Mark Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Daniel Borkowski , Vivek Garg , Cagdas Akturan , Avinash N. Ananthakrishnan
CPC分类号： G06F9/5094 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有功率控制器的多核处理器，所述功率控制器具有在处理器的利用率超过阈值水平时将功率管理策略从功率偏置策略动态切换到性能偏差策略的逻辑。 因此，在低利用率下，可以实现降低的功率消耗，而在更高的利用率下，可以实现更高的性能。 描述和要求保护其他实施例。
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10.发明申请PROCESSOR HAVING FREQUENCY OF OPERATION INFORMATION FOR GUARANTEED OPERATION UNDER HIGH TEMPERATURE EVENTS 有权具有运行信息频率的处理器，用于在高温事件下进行有担保的操作公开(公告)号：US20140281445A1
公开(公告)日：2014-09-18
申请号：US13843855
申请日：2013-03-15
申请人： Ankush Varma , Robin A. Steinbrecher , Susan F. Smith , Sandeep Ahuja , Vivek Garg , Tessil Thomas , Krishnakanth V. Sistla , Chris Poirier , Martin Mark T. Rowland
发明人： Ankush Varma , Robin A. Steinbrecher , Susan F. Smith , Sandeep Ahuja , Vivek Garg , Tessil Thomas , Krishnakanth V. Sistla , Chris Poirier , Martin Mark T. Rowland
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/20 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/16
摘要： A processor is described having a semiconductor chip having non volatile storage circuitry. The non volatile storage circuitry has information identifying a maximum operational frequency of the processor at which the processor's operation is guaranteed for an ambient temperature that corresponds to an extreme thermal event.
摘要翻译： 描述了具有具有非易失性存储电路的半导体芯片的处理器。 非易失性存储电路具有识别处理器的最大工作频率的信息，在该处理器处理器的操作被保证对应于极端热事件的环境温度。
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