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    METHOD OF OPTIMIZING SIDEWALL SPACER SIZE FOR SILICIDE PROXIMITY WITH IN-SITU CLEAN
    3.
    发明申请
    METHOD OF OPTIMIZING SIDEWALL SPACER SIZE FOR SILICIDE PROXIMITY WITH IN-SITU CLEAN 有权
    利用现场清洁优化硅酸盐污染物尺寸的方法

    公开(公告)号：US20090286389A1

    公开(公告)日：2009-11-19

    申请号：US12122840

    申请日：2008-05-19

    申请人： David G. Farber ,  Fred Hause ,  Markus Lenski ,  Anthony C. Mowry

    发明人： David G. Farber ,  Fred Hause ,  Markus Lenski ,  Anthony C. Mowry

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L29/6653 ,  H01L29/78

    摘要： A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.

    摘要翻译： 一种方法，包括在衬底上形成半导体器件的栅极，并且蚀刻栅极侧面上的侧壁间隔物以提供接近值，其中接近值被定义为栅极与性能增强的边缘之间的距离 地区。 侧壁间隔件用于在衬底中形成区域期间限定区域的边缘。 该方法还包括预先清洁栅极和基板以准备形成区域，其中在连续真空中进行蚀刻和预清洁。

    Method of optimizing sidewall spacer size for silicide proximity with in-situ clean
    4.
    发明授权
    Method of optimizing sidewall spacer size for silicide proximity with in-situ clean 有权
    用于原位清洁优化硅化物接近的侧壁间隔尺寸的方法

    公开(公告)号：US07745337B2

    公开(公告)日：2010-06-29

    申请号：US12122840

    申请日：2008-05-19

    申请人： David G. Farber ,  Fred Hause ,  Markus Lenski ,  Anthony C. Mowry

    发明人： David G. Farber ,  Fred Hause ,  Markus Lenski ,  Anthony C. Mowry

    IPC分类号： H01L21/311

    CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L29/6653 ,  H01L29/78

    摘要： A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.

    摘要翻译： 一种方法，包括在衬底上形成半导体器件的栅极，并且蚀刻栅极侧面上的侧壁间隔物以提供接近值，其中接近值被定义为栅极与性能增强的边缘之间的距离 地区。 侧壁间隔件用于在衬底中形成区域期间限定区域的边缘。 该方法还包括预先清洁栅极和基板以准备形成区域，其中在连续真空中进行蚀刻和预清洁。

    Method for selectively forming strain in a transistor by a stress memorization technique without adding additional lithography steps
    9.
    发明授权
    Method for selectively forming strain in a transistor by a stress memorization technique without adding additional lithography steps 有权
    通过应力存储技术在晶体管中选择性地形成应变的方法，而不添加额外的光刻步骤

    公开(公告)号：US07906385B2

    公开(公告)日：2011-03-15

    申请号：US12179116

    申请日：2008-07-24

    申请人： Markus Lenski ,  Frank Wirbeleit ,  Anthony Mowry

    发明人： Markus Lenski ,  Frank Wirbeleit ,  Anthony Mowry

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7847

    摘要： A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps.

    摘要翻译： 公开了选择性应力记忆技术，其中通过使用注入掩模或在标准制造流程期间所需的任何其它掩模，或通过提供用于应变重结晶的图案化盖层，可以在没有附加光刻步骤的情况下实现拉伸应变 的排水和源区。 在其它方面，可以使用附加的退火步骤，以在基于盖层的重结晶之前选择性地产生晶体状态和非晶态。 因此，可以在一种类型的晶体管中获得增强的应变，而不需要额外的光刻步骤基本上不影响其他类型的晶体管。