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1.发明授权公开(公告)号：US07541222B2
公开(公告)日：2009-06-02
申请号：US11530802
申请日：2006-09-11
CPC分类号： H01L23/3121 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/2919 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/48599 , H01L2224/48699 , H01L2224/48992 , H01L2224/49171 , H01L2224/73265 , H01L2224/85201 , H01L2224/85205 , H01L2224/8592 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/3862 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/85399 , H01L2224/05599
摘要： A method for manufacturing a wire sweep resistant semiconductor package provides a die attached to an interposer. The die is electrically connected to the interposer with conductive wires. A sealant is applied on the die at the conductive wires for preventing wire sweep and the sealant is free of contact with the interposer. The die, the interposer, the conductive wires, and the sealant are encapsulated in an encapsulant.
摘要翻译： 一种用于制造抗线扫描半导体封装件的方法提供附接到插入件的管芯。 管芯通过导线与插入器电连接。 在导线上的模具上施加密封剂以防止电线扫掠，并且密封剂与插入件不接触。 模具，插入件，导线和密封剂被封装在密封剂中。
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公开(公告)号：US07141886B2
公开(公告)日：2006-11-28
申请号：US11215090
申请日：2005-08-29
IPC分类号： H01L23/28
CPC分类号： H01L21/565 , H01L23/3121 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/16151 , H01L2224/32225 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A die is attached to a substrate and is enclosed in a heat spreader, the heat spreader having a first encapsulant guide and a heat spreader air vent in the heat spreader extending therethrough. An encapsulant encapsulates the die, the substrate, at least a portion of the heat spreader, the first encapsulant guide, and the heat spreader air vent such that the encapsulant enters the heat spreader through the first encapsulant guide and air exits the heat spreader through the heat spreader air vent, thus preventing the formation of air pockets under the heat spreader.
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公开(公告)号：US06969640B1
公开(公告)日：2005-11-29
申请号：US10934129
申请日：2004-09-02
CPC分类号： H01L21/565 , H01L23/3121 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/16151 , H01L2224/32225 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A die is attached to a substrate and is enclosed in a heat spreader, the heat spreader having a first encapsulant guide and a heat spreader air vent in the heat spreader extending therethrough. An encapsulant encapsulates the die, the substrate, at least a portion of the heat spreader, the first encapsulant guide, and the heat spreader air vent such that the encapsulant enters the heat spreader through the first encapsulant guide and air exits the heat spreader through the heat spreader air vent, thus preventing the formation of air pockets under the heat spreader.
摘要翻译： 将模具附接到基底并且封闭在散热器中，散热器具有第一密封剂引导件和在其中延伸穿过的散热器中的散热器通风口。 密封剂封装模具，衬底，散热器的至少一部分，第一密封剂引导件和散热器通风口，使得密封剂通过第一密封剂引导件进入散热器，空气通过散热器通过 散热器通风口，从而防止在散热器下形成气泡。
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公开(公告)号：US08421197B2
公开(公告)日：2013-04-16
申请号：US13023244
申请日：2011-02-08
IPC分类号： H01L23/48 , H01L23/50 , H01L23/49 , H01L23/495
CPC分类号： H01L23/4951 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/49513 , H01L23/49548 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/27436 , H01L2224/2919 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/83191 , H01L2224/83856 , H01L2224/85 , H01L2224/92247 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system includes: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; and electrical interconnects bonded to the adhesion layer.
摘要翻译： 集成电路封装系统包括：半导体芯片; 半导体芯片上的应力消除层; 应力消除层上的粘附层; 以及结合到粘合层的电互连。
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公开(公告)号：US20110121466A1
公开(公告)日：2011-05-26
申请号：US13023244
申请日：2011-02-08
CPC分类号： H01L23/4951 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/49513 , H01L23/49548 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/27436 , H01L2224/2919 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/83191 , H01L2224/83856 , H01L2224/85 , H01L2224/92247 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system includes: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; and electrical interconnects bonded to the adhesion layer.
摘要翻译： 集成电路封装系统包括：半导体芯片; 半导体芯片上的应力消除层; 应力消除层上的粘附层; 以及结合到粘合层的电互连。
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公开(公告)号：US20090079049A1
公开(公告)日：2009-03-26
申请号：US11858554
申请日：2007-09-20
IPC分类号： H01L23/495
CPC分类号： H01L23/4951 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/49513 , H01L23/49548 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/27436 , H01L2224/2919 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/83191 , H01L2224/83856 , H01L2224/85 , H01L2224/92247 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system includes: providing an integrated circuit wafer having an active side and a backside; forming a stress-relieving layer on the backside; forming an adhesion layer on the stress-relieving layer; dicing the integrated circuit wafer into a semiconductor chip with the stress-relieving layer and the adhesion layer on the backside of the semiconductor chip; and mounting the semiconductor chip over electrical interconnects.
摘要翻译： 集成电路封装系统包括：提供具有有源侧和背面的集成电路晶片; 在背面形成应力消除层; 在应力消除层上形成粘合层; 将集成电路晶片切割成具有应力消除层和半导体芯片的背面上的粘合层的半导体芯片; 并将半导体芯片安装在电气互连上。
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7.发明授权Method of manufacturing integrated circuit package system with warp-free chip 有权具有无翘曲芯片的集成电路封装系统的制造方法公开(公告)号：US07892894B2
公开(公告)日：2011-02-22
申请号：US11858554
申请日：2007-09-20
IPC分类号： H01L21/00
CPC分类号： H01L23/4951 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/49513 , H01L23/49548 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/27436 , H01L2224/2919 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/83191 , H01L2224/83856 , H01L2224/85 , H01L2224/92247 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system includes: providing an integrated circuit wafer having an active side and a backside; forming a stress-relieving layer on the backside; forming an adhesion layer on the stress-relieving layer; dicing the integrated circuit wafer into a semiconductor chip with the stress-relieving layer and the adhesion layer on the backside of the semiconductor chip; and mounting the semiconductor chip over electrical interconnects.
摘要翻译： 集成电路封装系统包括：提供具有有源侧和背面的集成电路晶片; 在背面形成应力消除层; 在应力消除层上形成粘合层; 将集成电路晶片切割成具有应力消除层和半导体芯片的背面上的粘合层的半导体芯片; 并将半导体芯片安装在电气互连上。
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8.发明申请公开(公告)号：US20060043612A1
公开(公告)日：2006-03-02
申请号：US10934835
申请日：2004-09-02
申请人： Sheila Magno , Byung Tai Do , Dennis Guillermo , Antonio Dimaano
发明人： Sheila Magno , Byung Tai Do , Dennis Guillermo , Antonio Dimaano
IPC分类号： H01L23/52
CPC分类号： H01L23/3121 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/2919 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/48599 , H01L2224/48699 , H01L2224/48992 , H01L2224/49171 , H01L2224/73265 , H01L2224/85201 , H01L2224/85205 , H01L2224/8592 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/3862 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/85399 , H01L2224/05599
摘要： A method for manufacturing a wire sweep resistant semiconductor package provides a die attached to an interposer. The die is electrically connected to the interposer with conductive wires. A sealant is applied to the conductive wires and optionally the die to prevent wire sweep, the sealant being applied free of contact with the interposer. The die, the interposer, the conductive wires, and the sealant are enclosed in an encapsulant.
摘要翻译： 一种用于制造抗线扫描半导体封装件的方法提供附接到插入件的管芯。 管芯通过导线与插入器电连接。 将密封剂施加到导电线和任选的模具以防止电线扫掠，密封剂被施加而不与插入物接触。 芯片，插入件，导线和密封剂封装在密封剂中。
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9.发明申请公开(公告)号：US20070063354A1
公开(公告)日：2007-03-22
申请号：US11530802
申请日：2006-09-11
CPC分类号： H01L23/3121 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/2919 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/48599 , H01L2224/48699 , H01L2224/48992 , H01L2224/49171 , H01L2224/73265 , H01L2224/85201 , H01L2224/85205 , H01L2224/8592 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/3862 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/85399 , H01L2224/05599
摘要： A method for manufacturing a wire sweep resistant semiconductor package provides a die attached to an interposer. The die is electrically connected to the interposer with conductive wires. A sealant is applied on the die at the conductive wires for preventing wire sweep and the sealant is free of contact with the interposer. The die, the interposer, the conductive wires, and the sealant are encapsulated in an encapsulant.
摘要翻译： 一种用于制造抗线扫描半导体封装件的方法提供附接到插入件的管芯。 管芯通过导线与插入器电连接。 在导线上的模具上施加密封剂以防止电线扫掠，并且密封剂与插入件不接触。 模具，插入件，导线和密封剂被封装在密封剂中。
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公开(公告)号：US10388584B2
公开(公告)日：2019-08-20
申请号：US13225683
申请日：2011-09-06
申请人： Reza A. Pagaila , Byung Tai Do , Linda Pei Ee Chua
发明人： Reza A. Pagaila , Byung Tai Do , Linda Pei Ee Chua
IPC分类号： H01L23/31 , H01L21/56 , H04B1/00 , H04B7/14 , H01L23/00 , H01L23/498 , H01L23/538 , H01L25/065 , H01L25/00 , H01L25/10 , H01L23/29 , H01L25/03
摘要： A semiconductor device has a temporary layer, such as a dam material or adhesive layer, formed over a carrier. A plurality of recesses is formed in the temporary layer. A first semiconductor die is mounted within the recesses of the temporary layer. An encapsulant is deposited over the first semiconductor die and temporary layer. The encapsulant extends into the recesses in the temporary layer. The carrier and temporary layer are removed to form recessed interconnect areas around the first semiconductor die. Alternatively, the recessed interconnect areas can be formed the carrier or encapsulant. Multiple steps can be formed in the recesses of the temporary layer. A conductive layer is formed over the first semiconductor die and encapsulant and into the recessed interconnect areas. A second semiconductor die can be mounted on the first semiconductor die. The semiconductor device can be integrated into PiP and Fi-PoP arrangements.
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