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公开(公告)号：US11043953B2
公开(公告)日：2021-06-22
申请号：US16866445
申请日：2020-05-04
Applicant: Apple Inc.
Inventor： Joachim S. Hammerschmidt , Robert G. Lorenz
Abstract: A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.
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2.发明公开公开(公告)号：US20240045080A1
公开(公告)日：2024-02-08
申请号：US17882422
申请日：2022-08-05
Applicant: Apple Inc.
Inventor： Glenn D. MacGougan , Robert G. Lorenz , Kevin X. Chin , William J. Bencze
Abstract: User equipment receives a GNSS signal that includes a GNSS signal from a satellite. The user equipment also receives a first data input from a motion sensor of the user equipment that is indicative of a motion of the user equipment, receives a second data input from the temperature sensor of the user equipment that is indicative of a temperature of the user equipment, and performs a coherent operation based on the pilot channel of the GNSS signal over a coherent period of time based on the first data input and the second data input to generate a resulting signal. The user equipment performs a non-coherent operation based on the resulting signal to amplify the resulting signal, and outputs a position of the user equipment based on the resulting signal.
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Patent Agency Ranking
3.发明授权公开(公告)号：US11481224B2
公开(公告)日：2022-10-25
申请号：US16557357
申请日：2019-08-30
Applicant: Apple Inc.
Inventor： Tao Mai , Robert G. Lorenz , Joachim S. Hammerschmidt , Utku Seckin
Abstract: A digital filter according to the disclosure includes a processing circuit having a memory and a number of parallel processing circuits. The parallel processing circuits perform a convolution operations based on input data and function data that is accessed from the memory. The filter further includes a serializer for serializing data that is received from the processing circuits. A clock generator circuit provides a first clock signal to the processing circuit and a second clock signal to the serializer. The frequency of the second clock signal is greater than that of the first clock signal.
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公开(公告)号：US20180097521A1
公开(公告)日：2018-04-05
申请号：US15676080
申请日：2017-08-14
Applicant: Apple Inc.
Inventor： Joachim S. Hammerschmidt , Robert G. Lorenz
CPC classification number: H03L7/0893 , H03B5/1243 , H03B5/1265 , H03B2201/025 , H03B2201/0266 , H03C3/0925 , H03C3/0933 , H03C3/095 , H03C3/0958 , H03C3/0991 , H03J2200/10 , H03L7/0805 , H03L7/0996 , H03L7/104 , H03L7/105 , H03L7/18 , H03L7/189 , H03L2207/06
Abstract: A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.
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5.发明申请公开(公告)号：US20210064380A1
公开(公告)日：2021-03-04
申请号：US16557357
申请日：2019-08-30
Applicant: Apple Inc.
Inventor： Tao Mai , Robert G. Lorenz , Joachim S. Hammerschmidt , Utku Seckin
Abstract: A digital filter according to the disclosure includes a processing circuit having a memory and a number of parallel processing circuits. The parallel processing circuits perform a convolution operations based on input data and function data that is accessed from the memory. The filter further includes a serializer for serializing data that is received from the processing circuits. A clock generator circuit provides a first clock signal to the processing circuit and a second clock signal to the serializer. The frequency of the second clock signal is greater than that of the first clock signal.
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公开(公告)号：US10749568B2
公开(公告)日：2020-08-18
申请号：US15674397
申请日：2017-08-10
Applicant: Apple Inc.
Inventor： Joachim S. Hammerschmidt , Robert G. Lorenz , Tad J. Dreier
IPC: H04B1/7156 , H04W72/04 , H04W4/80 , H04B1/713
Abstract: An electronic device that communicates with a second electronic device using adaptive frequency hopping across different spectral bands is described. An integrated circuit in the electronic device includes processing logic that determines an adaptive spectral map that specifies channels across multiple spectral bands. During communication with a second electronic device that includes a second integrated circuit using a communication protocol (such as Bluetooth or Bluetooth Low Energy), the integrated circuit selects channels in the adaptive spectral map, where selection can be based on a predefined frequency-hopping sequence.
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公开(公告)号：US10581447B1
公开(公告)日：2020-03-03
申请号：US16147531
申请日：2018-09-28
Applicant: Apple Inc.
Inventor： Simone Gambini , Robert G. Lorenz
Abstract: A method and apparatus for measuring phase response in a radio receiver is disclosed. A radio receiver includes a digital-to-analog (D/A) conversion unit coupled to receive a test signal. The D/A conversion unit includes a number of single-bit digital-to-analog conversion (DAC) circuits coupled to receive the test signal and configured to convert it into the analog domain. Clock signals received by each of the single-bit DAC circuits are out of phase with respect to one another. The output of the D/A conversion unit is an analog signal that is a composite of the signals output by the DAC circuits therein. The analog signal is then conveyed to an analog-to-digital converter (ADC) and converted into an N-bit digital signal. The N-bit digital signal is then conveyed to a correlator to determine a phase response of the radio receiver.
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