公开(公告)号：US10740527B2

公开(公告)日：2020-08-11

申请号：US15697239

申请日：2017-09-06

Applicant: Apple Inc.

Inventor： Farzan Farbiz ,  Thomas Hoffmann ,  Xin Yi Zhang

IPC: G06F30/30 ,  G06F30/392 ,  H01L27/118 ,  H01L27/092 ,  H01L29/78 ,  G06F30/33 ,  G06F30/39 ,  G06F30/394 ,  H01L27/02

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

公开(公告)号：US09929139B2

公开(公告)日：2018-03-27

申请号：US14641486

申请日：2015-03-09

Applicant: Apple Inc.

Inventor： Xiaofeng Fan ,  Xin Yi Zhang

IPC: H01L27/02 ,  H01L23/60 ,  H01L23/552

CPC classification number: H01L27/0255 ,  H01L23/552 ,  H01L23/60 ,  H01L27/0288 ,  H01L27/0292

Abstract: In an embodiment, an integrated circuit (IC) may include a circuit block that couples to one or more pins of the IC to communicate and/or receive power on the pins. The circuit block may include a ground connection, which may be electrically insulated/electrically separate from the ground connection of other components of the integrated circuit. In an embodiment, the circuit block may include an ESD protection circuit for the pad coupled to the pin. The IC may include another ESD protection circuit for the pad. The circuit block's ESD protection circuit may be sized for the current that may produced within the circuit block for an ESD event, and the IC's ESD protection circuit may be sized for the current that may be produced from the other components of the IC.

公开(公告)号：US09601480B2

公开(公告)日：2017-03-21

申请号：US14684841

申请日：2015-04-13

Applicant: Apple Inc.

Inventor： Junjun Li ,  Xin Yi Zhang ,  Xiaofeng Fan

IPC: H02H9/00 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0262 ,  H01L27/0255 ,  H01L29/785

Abstract: In an embodiment, an ESD protection circuit may include a silicon-controlled rectifier (SCR) and a diode sharing a PN junction and forming a bi-directional ESD circuit. The single PN junction may reduce the capacitive load on the pin, which may allow the high speed circuit to meet its performance goals. In an embodiment, a floating P-well contact may be placed between two neighboring SCRs, to control triggering of the SCRs.

公开(公告)号：US20160056147A1

公开(公告)日：2016-02-25

申请号：US14684841

申请日：2015-04-13

Applicant: Apple Inc.

Inventor： Junjun Li ,  Xin Yi Zhang ,  Xiaofeng Fan

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0262 ,  H01L27/0255 ,  H01L29/785

Abstract: In an embodiment, an ESD protection circuit may include a silicon-controlled rectifier (SCR) and a diode sharing a PN junction and forming a bi-directional ESD circuit. The single PN junction may reduce the capacitive load on the pin, which may allow the high speed circuit to meet its performance goals. In an embodiment, a floating P-well contact may be placed between two neighboring SCRs, to control triggering of the SCRs.

Abstract translation: 在一个实施例中，ESD保护电路可以包括可控硅整流器（SCR）和共享PN结的二极管并形成双向ESD电路。 单个PN结可能会降低引脚上的容性负载，这可能使高速电路达到其性能目标。 在一个实施例中，可以在两个相邻SCR之间放置浮动P阱接触，以控制SCR的触发。

公开(公告)号：US09653448B2

公开(公告)日：2017-05-16

申请号：US14533187

申请日：2014-11-05

Applicant: Apple Inc.

Inventor： Xin Yi Zhang ,  Xiaofeng Fan ,  Junjun Li

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01L29/785

Abstract: In an embodiment, an ESD protection circuit is provided in which diodes may be formed between N+ and P+ diffusions within an insulated semiconductor region and in which additional diodes may be formed between adjacent insulated regions of opposite conduction type as well. The diodes may be used in parallel to form an ESD protection circuit, which may have low on resistance and may sink high ESD current per unit area. To support the formation of the ESD protection circuit, each silicon region may have alternating N+ and P+ diffusions, and adjacent silicon regions may have N+ and P+ diffusions alternating in opposite locations. That is a perpendicular drawn between the N+ diffusions of one adjacent region may intersect P+ diffusions in the other adjacent region, and vice versa.

公开(公告)号：US20160056146A1

公开(公告)日：2016-02-25

申请号：US14684872

申请日：2015-04-13

Applicant: Apple Inc.

Inventor： Junjun Li ,  Xin Yi Zhang ,  Xiaofeng Fan

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/74 ,  H01L29/10 ,  H01L27/06 ,  H01L27/088 ,  H01L29/744

CPC classification number: H01L27/0259 ,  H01L27/0262 ,  H01L27/0635 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/7416 ,  H01L29/7436 ,  H01L29/744

Abstract: In an embodiment, an ESD protection circuit may include an STI-bound SCR and a gated SCR that may be electrically in parallel with the STI-bound SCR. The gated SCR may be perpendicular to the STI-bound SCR in a plane of the semiconductor substrate. In an embodiment, the gated SCR may trigger more quickly and turn on more quickly than the STI-bound SCR. The STI-bound SCR may form the main current path for an ESD event. A low capacitive load with rapid response to ESD events may thus be formed. In an embodiment, the anode of the two SCRs may be shared.

Abstract translation: 在一个实施例中，ESD保护电路可以包括可以与STI结合的SCR并联的STI结合的SCR和门控SCR。 门控SCR可以在半导体衬底的平面中垂直于STI结合的SCR。 在一个实施例中，门控SCR可以比STI结合的SCR更快地触发并且更快地触发。 STI结合的SCR可以形成用于ESD事件的主电流路径。 因此可以形成具有对ESD事件的快速响应的低容性负载。 在一个实施例中，两个SCR的阳极可以共享。

公开(公告)号：US20160020203A1

公开(公告)日：2016-01-21

申请号：US14533187

申请日：2014-11-05

Applicant: Apple Inc.

Inventor： Xin Yi Zhang ,  Xiaofeng Fan ,  Junjun Li

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01L29/785

Abstract: In an embodiment, an ESD protection circuit is provided in which diodes may be formed between N+ and P+ diffusions within an insulated semiconductor region and in which additional diodes may be formed between adjacent insulated regions of opposite conduction type as well. The diodes may be used in parallel to form an ESD protection circuit, which may have low on resistance and may sink high ESD current per unit area. To support the formation of the ESD protection circuit, each silicon region may have alternating N+ and P+ diffusions, and adjacent silicon regions may have N+ and P+ diffusions alternating in opposite locations. That is a perpendicular drawn between the N+ diffusions of one adjacent region may intersect P+ diffusions in the other adjacent region, and vice versa.

Abstract translation: 在一个实施例中，提供ESD保护电路，其中可以在绝缘半导体区域内的N +和P +扩散之间形成二极管，并且可以在相邻导电类型的相邻绝缘区域之间形成附加二极管。 二极管可以并联使用以形成ESD保护电路，其可以具有低导通电阻并且可能吸收每单位面积的高ESD电流。 为了支持ESD保护电路的形成，每个硅区域可以具有交替的N +和P +扩散，并且相邻的硅区域可以在相对的位置上交替地具有N +和P +扩散。 这是在一个相邻区域的N +扩散之间绘制的垂线可以在另一相邻区域中相交P +扩散，反之亦然。

公开(公告)号：US20230409797A1

公开(公告)日：2023-12-21

申请号：US18337781

申请日：2023-06-20

Applicant: Apple Inc.

Inventor： Farzan Farbiz ,  Thomas Hoffmann ,  Xin Yi Zhang

IPC: G06F30/392 ,  H01L27/118 ,  H01L27/092 ,  H01L29/78 ,  G06F30/33 ,  G06F30/39 ,  G06F30/394

CPC classification number: G06F30/392 ,  H01L27/11807 ,  H01L27/0921 ,  H01L29/785 ,  G06F30/33 ,  G06F30/39 ,  G06F30/394 ,  H01L27/0251

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

公开(公告)号：US11720734B2

公开(公告)日：2023-08-08

申请号：US16920524

申请日：2020-07-03

Applicant: Apple Inc.

Inventor： Farzan Farbiz ,  Thomas Hoffmann ,  Xin Yi Zhang

IPC: G06F30/392 ,  H01L27/118 ,  H01L27/092 ,  H01L29/78 ,  G06F30/33 ,  G06F30/39 ,  G06F30/394 ,  H01L27/02

CPC classification number: G06F30/392 ,  G06F30/33 ,  G06F30/39 ,  G06F30/394 ,  H01L27/0921 ,  H01L27/11807 ,  H01L29/785 ,  H01L27/0251 ,  H01L2027/1189

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

公开(公告)号：US20190073440A1

公开(公告)日：2019-03-07

申请号：US15697239

申请日：2017-09-06

Applicant: Apple Inc.

Inventor： Farzan Farbiz ,  Thomas Hoffmann ,  Xin Yi Zhang

IPC: G06F17/50

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.