公开(公告)号：US20230223256A1

公开(公告)日：2023-07-13

申请号：US17572963

申请日：2022-01-11

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Raman Gaire ,  Tyler Sherwood ,  Lan Yu ,  Roger Quon ,  Siddarth Krishnan

IPC: H01L21/02

CPC classification number: H01L21/02576 ,  H01L21/02579 ,  H01L21/02532

Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.

公开(公告)号：US20240282813A1

公开(公告)日：2024-08-22

申请号：US18171119

申请日：2023-02-17

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Raman Gaire ,  Roger Quon ,  Siddarth Krishnan

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/0649 ,  H01L29/66712 ,  H01L29/7802

Abstract: A super junction device with an increased manufacturing throughput may be formed by forming narrow trenches lined with a P-type liner and rapidly filled with a passive fill material. Instead of etching trenches with aspect ratio large enough to reliably fill with doped P-type material, the aspect ratio of the trench may be reduced to shrink the size of the device. This smaller trench may then be lined with a relatively thin (e.g., about 1 μm to about 2 μm) P-type liner instead of completely filling the trench with P-type material. Inside the P-type liner, the trench may then be filled with a passive fill material. Filling the trench with the passive fill material may be carried out in a matter of minutes at relatively high temperatures, thereby likely causing a void or seam to form within the passive fill material. However, because the passive fill material does not affect the operation of the device, this type of defect can exist in the device.

公开(公告)号：US20220310531A1

公开(公告)日：2022-09-29

申请号：US17214411

申请日：2021-03-26

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Lan Yu ,  Joseph F. Salfelder ,  Ki Cheol Ahn ,  Tyler Sherwood ,  Siddarth Krishnan ,  Michael Jason Fronckowiak ,  Xing Chen

IPC: H01L23/00 ,  H01L21/311 ,  H01L21/308 ,  H01L21/304

Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.

公开(公告)号：US11830824B2

公开(公告)日：2023-11-28

申请号：US17214411

申请日：2021-03-26

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Lan Yu ,  Joseph F. Salfelder ,  Ki Cheol Ahn ,  Tyler Sherwood ,  Siddarth Krishnan ,  Michael Jason Fronckowiak ,  Xing Chen

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/3086 ,  H01L21/31111

Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.

公开(公告)号：US11769665B2

公开(公告)日：2023-09-26

申请号：US17572963

申请日：2022-01-11

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Raman Gaire ,  Tyler Sherwood ,  Lan Yu ,  Roger Quon ,  Siddarth Krishnan

IPC: H01L21/02

CPC classification number: H01L21/02576 ,  H01L21/02532 ,  H01L21/02579

Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.