公开(公告)号：US20230223256A1

公开(公告)日：2023-07-13

申请号：US17572963

申请日：2022-01-11

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Raman Gaire ,  Tyler Sherwood ,  Lan Yu ,  Roger Quon ,  Siddarth Krishnan

IPC: H01L21/02

CPC classification number: H01L21/02576 ,  H01L21/02579 ,  H01L21/02532

Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.

公开(公告)号：US11536708B2

公开(公告)日：2022-12-27

申请号：US16738629

申请日：2020-01-09

Applicant: Applied Materials, Inc.

Inventor： Mark J. Saly ,  Keenan Navarre Woods ,  Joseph R. Johnson ,  Bhaskar Jyoti Bhuyan ,  William J. Durand ,  Michael Chudzik ,  Raghav Sreenivasan ,  Roger Quon

IPC: B82Y15/00 ,  B82Y40/00 ,  G01N33/487 ,  B01D67/00 ,  C12Q1/6869

Abstract: Embodiments of the present disclosure provide dual pore sensors and methods for producing these dual pore sensors. The method includes forming a film stack, where the film stack contains two silicon layers and two membrane layers, and then etching the film stack to produce a channel extending therethrough and having two reservoirs and two nanopores. The method also includes depositing a oxide layer on inner surfaces of the reservoirs and nanopores, depositing a dielectric layer on the oxide layer, and forming a metal contact extending through a portion of the stack. The method further includes etching the dielectric layers to form wells, etching the first silicon layer to reveal the protective oxide layer deposited on the inner surfaces of a reservoir, and etching the protective oxide layer deposited on the inner surfaces of the reservoirs and the nanopores.

公开(公告)号：US11819847B2

公开(公告)日：2023-11-21

申请号：US16933597

申请日：2020-07-20

Applicant: Applied Materials, Inc.

Inventor： Ryan Scott Smith ,  Roger Quon ,  David Collins ,  George Odlum ,  Raghav Sreenivasan ,  Joseph R. Johnson

IPC: B01L3/00 ,  B82B1/00 ,  B82B3/00 ,  G01N27/447 ,  G01N33/487 ,  G01N27/40

CPC classification number: B01L3/502753 ,  B82B1/005 ,  B82B3/008 ,  G01N27/40 ,  G01N27/44791 ,  G01N33/48721 ,  B01L2200/0647 ,  B01L2300/0896 ,  B01L2300/12

Abstract: Embodiments of the present disclosure provide nanopore devices, such as nanopore sensors and/or other nanofluidic devices. In one or more embodiments, a nanopore device contains a substrate, an optional lower protective oxide layer disposed on the substrate, a membrane disposed on the lower protective oxide layer, and an optional upper protective oxide layer disposed on the membrane. The membrane has a pore and contains silicon nitride. The silicon nitride has a nitrogen to silicon ratio of about 0.98 to about 1.02 and the membrane has an intrinsic stress value of about −1,000 MPa to about 1,000 MPa. The nanopore device also contains a channel extending through at least the substrate, the lower protective oxide layer, the membrane, the upper protective oxide layer, and the upper protective silicon nitride layer.

公开(公告)号：US11769665B2

公开(公告)日：2023-09-26

申请号：US17572963

申请日：2022-01-11

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Raman Gaire ,  Tyler Sherwood ,  Lan Yu ,  Roger Quon ,  Siddarth Krishnan

IPC: H01L21/02

CPC classification number: H01L21/02576 ,  H01L21/02532 ,  H01L21/02579

Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.

公开(公告)号：US11249067B2

公开(公告)日：2022-02-15

申请号：US16573540

申请日：2019-09-17

Applicant: Applied Materials, Inc.

Inventor： Joseph R. Johnson ,  Roger Quon

IPC: H01L21/00 ,  G01N33/487 ,  B81B1/00 ,  B81C3/00

Abstract: Nanopore flow cells and methods of manufacturing thereof are provided herein. In one embodiment a method of forming a flow cell includes forming a multi-layer stack on a first substrate, e.g., a monocrystalline silicon substrate, before transferring the multi-layer stack to a second substrate, e.g., a glass substrate. Here, the multi-layer stack features a membrane layer, having a first opening formed therethrough, where the membrane layer is disposed on the first substrate, and a material layer is disposed on the membrane layer. The method further includes patterning the second substrate to form a second opening therein and bonding the patterned surface of the second substrate to a surface of the multi-layer stack. The method further includes thinning the first substrate and thinning the second substrate. Here, the second substrate is thinned to where the second opening is disposed therethrough. The method further includes removing the thinned first substrate and at least portions of the material layer to expose opposite surfaces of the membrane layer.

公开(公告)号：US20240282813A1

公开(公告)日：2024-08-22

申请号：US18171119

申请日：2023-02-17

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Raman Gaire ,  Roger Quon ,  Siddarth Krishnan

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/0649 ,  H01L29/66712 ,  H01L29/7802

Abstract: A super junction device with an increased manufacturing throughput may be formed by forming narrow trenches lined with a P-type liner and rapidly filled with a passive fill material. Instead of etching trenches with aspect ratio large enough to reliably fill with doped P-type material, the aspect ratio of the trench may be reduced to shrink the size of the device. This smaller trench may then be lined with a relatively thin (e.g., about 1 μm to about 2 μm) P-type liner instead of completely filling the trench with P-type material. Inside the P-type liner, the trench may then be filled with a passive fill material. Filling the trench with the passive fill material may be carried out in a matter of minutes at relatively high temperatures, thereby likely causing a void or seam to form within the passive fill material. However, because the passive fill material does not affect the operation of the device, this type of defect can exist in the device.