公开(公告)号：US20240363357A1

公开(公告)日：2024-10-31

申请号：US18631384

申请日：2024-04-10

Applicant: Applied Materials, Inc.

Inventor： David H. Collins ,  Nobuyuki Takahashi ,  Pin Hian Lee ,  Rio Soedibyo ,  Sanggil Bae ,  Houssam Lazkani ,  Songkram Sonny Srivathanakul ,  Raman Gaire ,  Gopal Bajaj

IPC: H01L21/311 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L21/31105 ,  H01L21/0217 ,  H01L21/02274 ,  H01L23/562

Abstract: Embodiments of the present technology may include semiconductor processing methods. The methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-containing precursor and a nitrogen-containing precursor. A substrate including one or more materials may be disposed within the processing region. The substrate may be characterized by a first bowing of the substrate. The methods may include generating plasma effluents of the deposition precursors. The methods may include forming a layer of silicon-and-nitrogen-containing material on the substrate. The layer of silicon-and-nitrogen-containing material may be characterized by a tensile stress. Subsequent forming the layer of silicon-and-nitrogen-containing material, the substrate may be characterized by a second bowing of the substrate that is less than the first bowing of the substrate.

公开(公告)号：US20240407170A1

公开(公告)日：2024-12-05

申请号：US18659256

申请日：2024-05-09

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Raman Gaire ,  Hsueh Chung Chen ,  In Soo Jung ,  Houssam Lazkani ,  Hui Zhao ,  Liu Jiang ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi

IPC: H10B43/40 ,  H10B41/35 ,  H10B41/49 ,  H10B43/23 ,  H10B43/35

Abstract: Methods and structures to achieve low voltage (LV) and high voltage (HV) scale-down by suppressing the short channel effect of LV as well as increasing breakdown voltage of HV transistor are provided. A semiconductor device comprises a first transistor comprising a first well region of a first conductivity type, a first gate region disposed above the first well region, and a first contact region including a first epitaxial semiconductor adjacent to the first gate region; and a second transistor comprising a second well region of a second conductivity, a second gate region disposed above the second well region, and a second contact region including a second epitaxial semiconductor adjacent to the second gate region.

公开(公告)号：US12002705B2

公开(公告)日：2024-06-04

申请号：US17670777

申请日：2022-02-14

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Houssam Lazkani ,  Raman Gaire ,  Mehul Naik ,  Kuan-Ting Liu

IPC: H01L21/74 ,  H01L21/02 ,  H01L23/528 ,  H01L23/535

CPC classification number: H01L21/743 ,  H01L21/02016 ,  H01L21/02365 ,  H01L23/5286 ,  H01L23/535

Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.