公开(公告)号：US20240046966A1

公开(公告)日：2024-02-08

申请号：US18366903

申请日：2023-08-08

Applicant: Applied Materials, Inc.

Inventor： Hsiang Yu Lee ,  Pradeep K. Subrahmanyan ,  Takaya Matsushita ,  Changwoo Sun

IPC: G11C5/06 ,  H10B43/20 ,  H10B43/35

CPC classification number: G11C5/063 ,  H10B43/20 ,  H10B43/35

Abstract: A three-dimensional (3D) NAND memory structure may include material layers arranged in a vertical stack including alternating horizontal insulating layers and wordline layers. The material layers may be etched to form a landing pad. A vertical wordline may extend through one or more of the horizontal wordline layers beneath the landing pad. The vertical wordline may be conductively connected to a top horizontal wordline, and the vertical wordline may be insulated from any of the horizontal wordlines that the vertical wordline extends through beneath the top horizontal wordline. A liner may also be formed over a top horizontal wordline at the landing pad.

公开(公告)号：US20230380170A1

公开(公告)日：2023-11-23

申请号：US18319876

申请日：2023-05-18

Applicant: Applied Materials, Inc.

Inventor： Hsiang Yu Lee ,  Pradeep K. Subrahmanyan

IPC: H10B43/35 ,  C30B29/06 ,  C30B29/16 ,  C30B29/38 ,  C30B29/68 ,  C30B33/08 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  C30B29/06 ,  C30B29/16 ,  C30B29/38 ,  C30B29/68 ,  C30B33/08 ,  H10B43/10 ,  H10B43/27

Abstract: A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.

公开(公告)号：US20240365545A1

公开(公告)日：2024-10-31

申请号：US18639572

申请日：2024-04-18

Applicant: Applied Materials, Inc.

Inventor： Hsiang Yu Lee ,  Pradeep K. Subrahmanyan

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a depth of the array of contact opening pairs varies in the first direction. The method may further include forming a second lithography mask over the film stack, and performing a second series of alternating lithography and etch processes, wherein an opening through the second lithography mask is expanded in a second direction following each etch process, and wherein the depth of the array of contact opening pairs varies in the second direction.

公开(公告)号：US20240363150A1

公开(公告)日：2024-10-31

申请号：US18640422

申请日：2024-04-19

Applicant: Applied Materials, Inc.

Inventor： Hsiang Yu Lee ,  Pradeep K. Subrahmanyan

IPC: G11C5/06 ,  G11C16/04 ,  H01L21/027 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: G11C5/063 ,  G11C16/0483 ,  H01L21/0274 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a depth of the array of contact opening pairs varies in the first direction. The method may further include forming a second lithography mask over the film stack, and performing a second series of alternating lithography and etch processes, wherein an opening through the second lithography mask is expanded in a second direction following each etch process, and wherein the depth of the array of contact opening pairs varies in the second direction.

公开(公告)号：US20230413569A1

公开(公告)日：2023-12-21

申请号：US18319869

申请日：2023-05-18

Applicant: Applied Materials, Inc.

Inventor： Hsiang Yu Lee ,  Pradeep K. Subrahmanyan

IPC: H10B43/35 ,  C30B29/06 ,  C30B29/38 ,  C30B29/16 ,  C30B29/68 ,  C30B33/08 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  C30B29/06 ,  C30B29/38 ,  H10B43/27 ,  C30B29/68 ,  C30B33/08 ,  H10B43/10 ,  C30B29/16

Abstract: A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.