公开(公告)号：US20220336223A1

公开(公告)日：2022-10-20

申请号：US17846155

申请日：2022-06-22

Applicant: Applied Materials, Inc.

Inventor： Yu Lei ,  Xuesong Lu ,  Tae Hong Ha ,  Xianmin Tang ,  Andrew Nguyen ,  Tza-Jing Gung ,  Philip A. Kraus ,  Chung Nang Liu ,  Hui Sun ,  Yufei Hu

IPC: H01L21/311 ,  H01L21/02 ,  H01J37/32 ,  H01L21/683 ,  H01L21/3105 ,  H01L21/67 ,  H01L21/8234

Abstract: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

公开(公告)号：US09741566B2

公开(公告)日：2017-08-22

申请号：US15043183

申请日：2016-02-12

Applicant: Applied Materials, Inc.

Inventor： Dai-Wen Tang ,  Hui Sun ,  Chung Liu ,  Benjamin Schwarz

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31122 ,  H01L21/32137 ,  Y10S438/947

Abstract: Embodiments herein provide apparatus and methods for performing an etching process on a spacer layer with good profile control in multiple patterning processes. In one embodiment, a method for patterning a spacer layer during a multiple patterning process includes conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has having a first group of openings defined therebetween and etching the spacer layer disposed on the substrate while forming an oxidation layer on the spacer layer.

公开(公告)号：US11562909B2

公开(公告)日：2023-01-24

申请号：US16881145

申请日：2020-05-22

Applicant: Applied Materials, Inc.

Inventor： Yu Lei ,  Xuesong Lu ,  Tae Hong Ha ,  Xianmin Tang ,  Andrew Nguyen ,  Tza-Jing Gung ,  Philip A. Kraus ,  Chung Nang Liu ,  Hui Sun ,  Yufei Hu

IPC: H01L21/67 ,  H01L21/311 ,  H01L21/02 ,  H01J37/32 ,  H01L21/683 ,  H01L21/3105 ,  H01L21/8234

Abstract: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

公开(公告)号：US20210366722A1

公开(公告)日：2021-11-25

申请号：US16881145

申请日：2020-05-22

Applicant: Applied Materials, Inc.

Inventor： Yu Lei ,  Xuesong Lu ,  Tae Hong Ha ,  Xianmin Tang ,  Andrew Nguyen ,  Tza-Jing Gung ,  Philip A. Kraus ,  Chung Nang Liu ,  Hui Sun ,  Yufei Hu

IPC: H01L21/311 ,  H01L21/02 ,  H01J37/32 ,  H01L21/683 ,  H01L21/3105 ,  H01L21/67 ,  H01L21/8234

Abstract: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.