公开(公告)号：US20250087573A1

公开(公告)日：2025-03-13

申请号：US18464926

申请日：2023-09-11

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Raghav Sreenivasan ,  Michael Chudzik ,  Maria Gorchichko

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/64

Abstract: The interconnect resistances in a hybrid bonded structure can be controlled and designed. The resistance of each interconnect can be controlled by the width of the vias, the number of vias, and the thickness of liners within the vias. A first interconnect and a second interconnect of a hybrid bonded structure can have different interconnect resistances despite being on the same wafer or chip. The techniques described herein include designing interconnects and forming interconnects with particular resistances.

公开(公告)号：US20220165912A1

公开(公告)日：2022-05-26

申请号：US17100402

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: H01L33/00 ,  G02F1/1362 ,  H01L33/62

Abstract: Processing methods may be performed to form a pixel material in a semiconductor substrate. The methods may include forming a lithographic mask overlying the semiconductor substrate. The lithographic mask may include a window. The method may include forming a via in the semiconductor substrate by a dry etch process through the window. The method may also include forming the pixel material by depositing a fill material in the via.

公开(公告)号：US20250079312A1

公开(公告)日：2025-03-06

申请号：US18460154

申请日：2023-09-01

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Raghav Sreenivasan ,  Kun Li

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/00

Abstract: A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface of the structure can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. For example, the dielectric constant of the dielectric film can be about or greater than 7 or 8. A semiconductor device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. A dielectric film-oxide-metal-substrate structure can be formed with the dielectric film on the top surface of the stack. A multi-material etch can be used etch features in the dielectric film and the oxide in a dielectric film-oxide-metal-substrate stack. A chemical-mechanical polishing technique can be used to precisely form the surface of the structure in preparation for hybrid bonding.

公开(公告)号：US11819847B2

公开(公告)日：2023-11-21

申请号：US16933597

申请日：2020-07-20

Applicant: Applied Materials, Inc.

Inventor： Ryan Scott Smith ,  Roger Quon ,  David Collins ,  George Odlum ,  Raghav Sreenivasan ,  Joseph R. Johnson

IPC: B01L3/00 ,  B82B1/00 ,  B82B3/00 ,  G01N27/447 ,  G01N33/487 ,  G01N27/40

CPC classification number: B01L3/502753 ,  B82B1/005 ,  B82B3/008 ,  G01N27/40 ,  G01N27/44791 ,  G01N33/48721 ,  B01L2200/0647 ,  B01L2300/0896 ,  B01L2300/12

Abstract: Embodiments of the present disclosure provide nanopore devices, such as nanopore sensors and/or other nanofluidic devices. In one or more embodiments, a nanopore device contains a substrate, an optional lower protective oxide layer disposed on the substrate, a membrane disposed on the lower protective oxide layer, and an optional upper protective oxide layer disposed on the membrane. The membrane has a pore and contains silicon nitride. The silicon nitride has a nitrogen to silicon ratio of about 0.98 to about 1.02 and the membrane has an intrinsic stress value of about −1,000 MPa to about 1,000 MPa. The nanopore device also contains a channel extending through at least the substrate, the lower protective oxide layer, the membrane, the upper protective oxide layer, and the upper protective silicon nitride layer.

公开(公告)号：US20230066610A1

公开(公告)日：2023-03-02

申请号：US17411599

申请日：2021-08-25

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Joseph F. Salfelder ,  Ki Cheol Ahn ,  Kai Ma ,  Raghav Sreenivasan ,  Jason Appell

IPC: H01L23/00

Abstract: Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.

公开(公告)号：US20250079356A1

公开(公告)日：2025-03-06

申请号：US18460174

申请日：2023-09-01

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Raghav Sreenivasan

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/67

Abstract: A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface can be used to form devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. The dielectric constant of the dielectric film can be about or greater than 8. A device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. A technique for forming the structure can include selectively depositing the dielectric film via atomic layer deposition after features filled with metal in a top layer of oxide in an oxide-metal-substrate stack. In order to selectively deposit the dielectric film, the metal may be covered with a polymer which can be burned off. A chemical-mechanical polishing technique can be used to precisely form the surface of the structure in preparation for hybrid bonding.

公开(公告)号：US20240321636A1

公开(公告)日：2024-09-26

申请号：US18186656

申请日：2023-03-20

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Raghav Sreenivasan

IPC: H01L21/768 ,  H01L23/373 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/7684 ,  H01L23/3736 ,  H01L23/53233 ,  H01L21/02068 ,  H01L21/67161 ,  H01L21/67207 ,  H01L21/76802 ,  H01L21/76843 ,  H01L23/53238

Abstract: The present technology includes semiconductor processing methods and devices with improved expansion of the bulk material in substrate features. Methods include cleaning a substrate that is formed from silicon oxide and that defines one or more features and that includes a liner that extends across the silicon oxide and within one or more features and a copper-containing layer deposited on the liner and extending within the one or more features. Methods include depositing a second metal over the substrate, where the second metal has a coefficient of thermal expansion of greater than or about 17. Methods also include diffusing the second metal into the copper containing layer to form a copper alloy.

公开(公告)号：US11880052B2

公开(公告)日：2024-01-23

申请号：US17100416

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02B5/08 ,  H01L33/46 ,  H01L23/48 ,  H01L33/10 ,  G02F1/1335 ,  G02F1/1362

CPC classification number: G02B5/0808 ,  H01L23/481 ,  H01L33/10 ,  H01L33/46 ,  G02F1/133553 ,  G02F1/136277

Abstract: Processing methods may be performed to form a grounded mirror structure on a semiconductor substrate. The methods may include revealing a metal layer. The metal layer may underlie a spacer layer. The metal layer may be revealed by a dry etch process. The method may include forming a mirror layer overlying the spacer layer and the metal layer. The mirror layer may contact the metal layer. The method may also include forming an oxide inclusion overlying a portion of the mirror layer. The portion of the mirror layer may be external to the spacer layer.

公开(公告)号：US11573452B2

公开(公告)日：2023-02-07

申请号：US17100422

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02F1/1335 ,  G02F1/1362

Abstract: Processing methods may be performed to forming a pixel material in a semiconductor structure. The methods may include forming a sacrificial hardmask overlying an uppermost layer of an optical stack of the semiconductor structure, the uppermost layer having a thickness. The methods may include forming a via through the sacrificial hardmask in the optical stack by a first etch process unselective to a metal layer of the semiconductor structure. The methods may include filling the via with a fill material, wherein a portion of the fill material extends over the sacrificial hardmask and contacts the metal layer. The methods may include removing a portion of the fill material external to the via by a removal process selective to the fill material. The methods may also include removing the sacrificial hardmask by a second etch process selective to the sacrificial hardmask while maintaining the thickness of the uppermost layer.

公开(公告)号：US11536708B2

公开(公告)日：2022-12-27

申请号：US16738629

申请日：2020-01-09

Applicant: Applied Materials, Inc.

Inventor： Mark J. Saly ,  Keenan Navarre Woods ,  Joseph R. Johnson ,  Bhaskar Jyoti Bhuyan ,  William J. Durand ,  Michael Chudzik ,  Raghav Sreenivasan ,  Roger Quon

IPC: B82Y15/00 ,  B82Y40/00 ,  G01N33/487 ,  B01D67/00 ,  C12Q1/6869

Abstract: Embodiments of the present disclosure provide dual pore sensors and methods for producing these dual pore sensors. The method includes forming a film stack, where the film stack contains two silicon layers and two membrane layers, and then etching the film stack to produce a channel extending therethrough and having two reservoirs and two nanopores. The method also includes depositing a oxide layer on inner surfaces of the reservoirs and nanopores, depositing a dielectric layer on the oxide layer, and forming a metal contact extending through a portion of the stack. The method further includes etching the dielectric layers to form wells, etching the first silicon layer to reveal the protective oxide layer deposited on the inner surfaces of a reservoir, and etching the protective oxide layer deposited on the inner surfaces of the reservoirs and the nanopores.