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公开(公告)号：US20150049118A1
公开(公告)日：2015-02-19
申请号：US14309487
申请日：2014-06-19
Applicant: ARM Limited
Inventor： Daren CROXFORD , Thomas James Cooksey , Sean Tristram Ellis
IPC: G06T11/60
CPC classification number: G06T11/60 , G06T11/40 , G06T15/005
Abstract: A graphics processing apparatus (2) performs tile based compositing operations. Tile metadata includes flag data (tfd), such as transparency and/or intensity flag data, indicating whether a given input graphics tile make less than a predetermined first threshold level of contribution or more than a second predetermined threshold level of contribution to a corresponding output graphics tile. For example, if an input graphics tile is transparent, then its reading from a memory (6) and/or subsequent processing may be suppressed. If a given input graphics tile is opaque, then any underlying input graphics tiles were are obscured may have their reading and/or further processing suppressed.
Abstract translation: 图形处理装置（2）执行基于瓦片的合成操作。 平铺元数据包括诸如透明度和/或强度标志数据的标志数据（tfd），其指示给定的输入图形图块是否小于预定的第一阈值贡献水平，或者大于对相应输出的第二预定阈值水平 图形瓦片。 例如，如果输入图形瓦片是透明的，则可以抑制其从存储器（6）的读取和/或后续处理。 如果给定的输入图形瓦片是不透明的，那么任何底层的输入图形瓦片被遮蔽可能会使其阅读和/或进一步的处理受到抑制。
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公开(公告)号：US10593305B2
公开(公告)日：2020-03-17
申请号：US15361751
申请日：2016-11-28
Applicant: ARM Limited
Inventor： Michal Karol Bogusz , Damian Piotr Modrzyk , Quinn Carter , Thomas James Cooksey
IPC: G06F12/0862 , G06F12/0875 , G06F12/1027 , G06T1/60 , G09G5/397 , G09G5/36 , G09G5/395 , G06T15/00
Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller.The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.
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公开(公告)号：US10719632B2
公开(公告)日：2020-07-21
申请号：US15246949
申请日：2016-08-25
Applicant: ARM Limited
Inventor： Håkan Lars-Göran Persson , Steven John Price , Thomas James Cooksey
IPC: G06F21/74 , G06F21/75 , G06F21/70 , G06F21/71 , H04L9/00 , G06F9/48 , G06F9/50 , C09D11/50 , C09B67/02 , G06F21/14 , G06F21/12 , G06F21/55 , G06F21/50 , G06F21/60 , G06F12/14 , H04L9/06 , G06F9/46 , G06T1/20
Abstract: A data processing system includes a host processor that executes an operating system and an accelerator operable to process data under the control of the operating system executing on the host processor. The accelerator can be switched between a normal mode of operation and a protected mode of operation in which the side channel information that can be provided by the accelerator to the host processor is restricted. The data processing system also includes a mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.
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公开(公告)号：US10115222B2
公开(公告)日：2018-10-30
申请号：US15401639
申请日：2017-01-09
Applicant: ARM Limited
Abstract: A graphics processing unit comprises a programmable execution unit executing graphics processing programs for execution threads to perform graphics processing operations, a local register memory comprising one or more registers, where registers of the register memory are assignable to store data associated with an individual execution thread that is being executed by the execution unit, and where the register(s) assigned to an individual execution thread are accessible only to that associated individual execution thread, and a further local memory that is operable to store data for use in common by plural execution threads, where the data stored in the further local memory is accessible to plural execution threads as they execute. The programmable execution unit is operable to selectively store output data for an execution thread in a register(s) of the local register memory assigned to the execution thread, and the further local memory.
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公开(公告)号：US20240249127A1
公开(公告)日：2024-07-25
申请号：US18349124
申请日：2023-07-08
Applicant: Arm Limited
Inventor： Thomas James Cooksey , Elliot Maurice Simon Rosemarine
IPC: G06N3/063
CPC classification number: G06N3/063
Abstract: A data processing system comprising a processor (306) that is configured to perform neural network processing having one or more execution units (213, 214) configured to perform processing operations for neural network processing and a control circuit (217) configured to distribute processing tasks to the execution unit or units, and a graphics processor (304) comprising a programmable execution unit (203) operable to execute processing programs to perform processing operations. The control circuit (217) of the processor (306) that is configured to perform neural network processing is configured to, in response to an indication of particular neural network processing to be performed provided to the control circuit, cause the programmable execution unit (203) of the graphics processor to execute a program to perform the indicated neural network processing.
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Patent Agency Ranking
公开(公告)号：US20170162179A1
公开(公告)日：2017-06-08
申请号：US15361751
申请日：2016-11-28
Applicant: ARM Limited
Inventor： Michal Karol Bogusz , Damian Piotr Modrzyk , Quinn Carter , Thomas James Cooksey
IPC: G09G5/397 , G09G5/36 , G06F12/1027 , G06F12/0862 , G06F12/0875
Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller.The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.
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公开(公告)号：US20170060637A1
公开(公告)日：2017-03-02
申请号：US15246949
申请日：2016-08-25
Applicant: ARM Limited
Inventor： Håkan Lars-Göran Persson , Steven John Price , Thomas James Cooksey
Abstract: A data processing system includes a host processor that executes an operating system and an accelerator operable to process data under the control of the operating system executing on the host processor. The accelerator can be switched between a normal mode of operation and a protected mode of operation in which the side channel information that can be provided by the accelerator to the host processor is restricted. The data processing system also includes a mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.
Abstract translation: 数据处理系统包括执行操作系统的主处理器和可操作以在主处理器上执行的操作系统的控制下处理数据的加速器。 加速器可以在正常操作模式和保护操作模式之间切换，其中加速器可以向主机处理器提供的侧信道信息被限制。 数据处理系统还包括用于将加速器从其正常操作模式切换到保护操作模式以及从保护操作模式到正常操作模式的机制。
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公开(公告)号：US11270412B2
公开(公告)日：2022-03-08
申请号：US16670344
申请日：2019-10-31
Applicant: Apical Limited , Arm Limited
Inventor： Alexey Kornienko , Maxim Novikov , Thomas James Cooksey , Jinhui He
Abstract: An image signal processor, comprising an input module for obtaining input data from a camera, whereby the camera is arranged to capture a representation of a real-world environment. The image signal processor further comprises at least one adjustment module for compressing the input data and producing compressed input data, and a localization and mapping module arranged to generate one or more data points from the compressed input data. The image signal processor also comprises an output module for outputting at least the one or more data points.
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公开(公告)号：US10936365B2
公开(公告)日：2021-03-02
申请号：US16062952
申请日：2016-12-15
Applicant: Arm Limited
Inventor： Samuel Martin , Thomas James Cooksey , Bobby Anirvan Batacharia
Abstract: When performing “time warp slice” rendering for a virtual reality display, the application rendering (30) of the images required for the application that requires the virtual reality display is synchronised (35) to the display frame rate and treated as a “normal” priority task (51) in terms of its scheduling on a host processor. The time warp slice rendering (50) to render the time warp “slices” into the display buffer (21) of the display (4) for scanning out (23) as the display panel is being refreshed is effected as a “real time” priority task (58). To do this, the rendering task setup processing that must be performed on the host processor for that rendering task is scheduled using an earliest deadline first scheduling policy and is synchronised (52) to specific, recurring display events (53) that allow the “real time” priority time warp slice rendering task setup processing on the host processor to be triggered at specific points in the scan out period (23) of the display (4).
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公开(公告)号：US20170206698A1
公开(公告)日：2017-07-20
申请号：US15401639
申请日：2017-01-09
Applicant: ARM Limited
CPC classification number: G06T15/005 , G06F8/41 , G06F8/454 , G06F8/458 , G06T15/80
Abstract: A graphics processing unit comprises a programmable execution unit executing graphics processing programs for execution threads to perform graphics processing operations, a local register memory comprising one or more registers, where registers of the register memory are assignable to store data associated with an individual execution thread that is being executed by the execution unit, and where the register(s) assigned to an individual execution thread are accessible only to that associated individual execution thread, and a further local memory that is operable to store data for use in common by plural execution threads, where the data stored in the further local memory is accessible to plural execution threads as they execute. The programmable execution unit is operable to selectively store output data for an execution thread in a register(s) of the local register memory assigned to the execution thread, and the further local memory.
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