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1.发明授权Method for converting an analog signal into a digital signal and electromagnetic radiation sensor using same 有权用于将模拟信号转换为数字信号的方法和使用其的电磁辐射传感器公开(公告)号：US06850176B2
公开(公告)日：2005-02-01
申请号：US10311077
申请日：2001-06-12
IPC分类号： H04N5/3745 , H03M1/00 , H03M1/12
CPC分类号： H04N5/37455 , H04N5/33
摘要： Device converts an analogue signal representing charges resulting from the photo-detection of electromagnetic radiation into a digital signal. Device includes (a) a number of photo-detectors connected in rows and columns through of buses, the photo-detectors in one column sharing the same column bus, itself connected to an output stage by through a row bus, and between each photo-detector and the column bus, (b) an integrator, to integrate the charges arriving from the photo-detector, (c) means for resetting the integrator, and (d) a comparator to compare the voltage Vp from the integrator with an internally predefined threshold voltage Vs, characterized in that it also includes a processing device, a clock, the clock controlling the processing device and the processing device receiving a binary value present at the output of the comparator at each signal from the clock.
摘要翻译： 设备将表示由电磁辐射的光检测产生的电荷的模拟信号转换为数字信号。 器件包括（a）通过总线以行和列连接的多个光电检测器，一列中的光电检测器共享相同的列总线，本身通过行总线连接到输出级， 检测器和列总线，（b）积分器，用于积分从光检测器到达的电荷，（c）用于复位积分器的装置，以及（d）比较器，用于将来自积分器的电压Vp与内部预定义 阈值电压Vs，其特征在于还包括处理装置，时钟，控制处理装置的时钟和处理装置，其接收来自时钟的每个信号处于比较器输出端的二进制值。
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公开(公告)号：US20050275448A1
公开(公告)日：2005-12-15
申请号：US11149216
申请日：2005-06-10
CPC分类号： H03K17/165 , G11C27/024
摘要： The invention relates to a method for controlling an analogue switch comprising a transistor, to which an input voltage Vin is applied, wherein: during a first phase, a first voltage, function of Vin and of a first potential V1, and that can make the transistor conduct, is applied to the transistor gate during a second phase, a second voltage, function of Vin and of a second potential V2, and that can block the transistor, is applied to the transistor gate, the difference between first voltage and second voltage being independent of Vin.
摘要翻译： 该方法包括在导通状态期间向晶体管（50）的栅极（51）施加电压，并且在断开状态期间向晶体管的栅极施加另一电压。 前一个电压是输入电压（Vin）和源极电压（Vdd）的总和，后一个电压是输入和电源电压之间的差值。 前一电压由电容器（42）施加，后一电压由电容器（44）施加。 - 还包括用于控制模拟开关的设备的独立权利要求。
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3.发明授权SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit 有权具有解耦能力的SOI型集成电路和用于这种电路实施例的工艺公开(公告)号：US06558998B2
公开(公告)日：2003-05-06
申请号：US10075382
申请日：2002-02-15
申请人： Marc Belleville , Michel Bruel
发明人： Marc Belleville , Michel Bruel
IPC分类号： H01L218238
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/76264 , H01L21/84 , H01L29/78606
摘要： Integrated circuit comprising: at least one first and one second power supply terminal (418, 420), at least one active area (302, 304, 306, 308) formed in a thin layer (206) of a substrate and electrically connected to at least one of the power supply terminals. According to the invention, the circuit also comprises capacitive decoupling means formed by at least one dielectric capacitor (110, 112, 114) connected between the said, first and second power supply terminals and formed in a region of the substrate that is electrically insulated from the thin substrate layer (206). Applications include the manufacture of portable electronic equipment.
摘要翻译： 集成电路，包括：至少一个第一和一个第二电源端子（418,420），形成在衬底的薄层（206）中并与之电连接的至少一个有源区域（302,304,306,308） 至少一个电源端子。根据本发明，电路还包括由连接在所述第一和第二电源端子之间的至少一个介电电容器（110,112,114）形成的电容去耦装置，并形成在一个区域 与薄基板层（206）电绝缘的基板。应用包括便携式电子设备的制造。
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公开(公告)号：US20120074982A1
公开(公告)日：2012-03-29
申请号：US13265207
申请日：2010-04-20
IPC分类号： H03K19/003
CPC分类号： G01R31/31725 , G01R31/3187
摘要： A digital electronic circuit includes: a plurality of sequential elements; at least one data-conducting path connecting an input sequential element to a destination sequential element; a clock outputting a clock signal on a clock tree for setting the speed of the sequential elements; a monitoring device receiving, as an input, at least one data signal traveling on a conducting path and arriving at a destination sequential element, the monitoring device including: a module for defining at least one detection window according to the clock tree; and a detector for detecting a transition of each data signal received during a detection window; and wherein each detection window is defined so as to enable the detection or anticipation of a fault corresponding to a violation of the rise time or the maintenance time of a data signal relative to a clock signal edge received by the destination sequential element receiving the data signal.
摘要翻译： 数字电子电路包括：多个顺序元件; 将输入顺序元素连接到目的地顺序元素的至少一个数据传导路径; 在时钟树上输出用于设定顺序元件的速度的时钟信号的时钟; 监视装置接收作为输入的至少一个在导电路径上行进并到达目的地顺序元件的数据信号，所述监视装置包括：用于根据所述时钟树定义至少一个检测窗口的模块; 以及检测器，用于检测在检测窗口期间接收的每个数据信号的转变; 并且其中每个检测窗被定义成使得能够检测或预测对应于数据信号相对于由接收数据信号的目的地顺序元件接收的时钟信号边缘的上升时间或维护时间的违反的故障 。
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5.发明授权公开(公告)号：US07622983B2
公开(公告)日：2009-11-24
申请号：US11687047
申请日：2007-03-16
IPC分类号： H03K3/01
CPC分类号： G05F3/205
摘要： A circuit for biasing the bulk of a MOS transistor, including a capacitive element connecting the bulk of the MOS transistor to a source of an voltage.
摘要翻译： 一种用于偏置MOS晶体管的体的电路，包括将MOS晶体管的主体连接到AC电压源的电容元件。
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公开(公告)号：US5912728A
公开(公告)日：1999-06-15
申请号：US810212
申请日：1997-02-28
申请人： Pascal Besesty , Marc Belleville
发明人： Pascal Besesty , Marc Belleville
摘要： This invention relates to a device for measuring the duration of a time interval between a start signal (D) and an end signal (F) comprising: a clock (H) supplying pulses with a period T, a digital circuit (2, 3, 4) to carry out a coarse measurement of the number of clock pulses between D and F, an analog circuit (6, 8, 10, 12, 14) to carry out a fine measurement of the time respectively between D and the first (respectively between F and the last) clock pulse which begins after D (respectively before F), this circuit comprising: means (8, 10) of generating N ramps with the same direction, means of sampling at least one the ramps at the instants that D and F occur. Application to a microlaser telemeter.
摘要翻译： 本发明涉及一种用于测量起始信号（D）和结束信号（F）之间的时间间隔的持续时间的装置，包括：提供具有周期T的脉冲的时钟（H），数字电路（2,3， 4）对D和F之间的时钟脉冲数量进行粗略测量，模拟电路（6,8,10,12,14）分别在D与第一（分别）之间执行时间的精细测量 在F和最后一个之间）在D（分别在F之前）开始的时钟脉冲之间，该电路包括：产生具有相同方向的N个斜坡的装置（8,10），在时刻采样至少一个斜坡的装置 和F发生。 应用于微型激光遥测仪。
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公开(公告)号：US4398155A
公开(公告)日：1983-08-09
申请号：US273815
申请日：1981-06-15
IPC分类号： H03K17/693 , H03K5/26 , H03L7/00
CPC分类号： H03K17/693
摘要： A circuit for switching between multiple asynchronous clocks is provided. A synchronizer comprising D-type flip-flops, which are controlled by a clock change signal, are provided for each control signal being switched. Output signals provided by the synchronizers are used to control MOS transistor gates which switch the asynchronous clocks to the circuit output. The synchronizers also control a clamping transistor gate which clamps the circuit output to a reference during a switching operation. An additional synchronizer provides synchronization between the clock change signal and the circuit output allowing the circuit output to be interrupted at a known state.
摘要翻译： 提供了一种用于在多个异步时钟之间切换的电路。 为被切换的每个控制信号提供包括由时钟变化信号控制的D型触发器的同步器。 由同步器提供的输出信号用于控制将异步时钟切换到电路输出的MOS晶体管栅极。 同步器还控制钳位晶体管栅极，其在开关操作期间将电路输出钳位到参考电压。 另外的同步器提供时钟变化信号和电路输出之间的同步，允许在已知状态下中断电路输出。
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8.发明授权Method and device for asynchronous communication of data on a single conductor 有权用于在单个导体上异步通信数据的方法和装置公开(公告)号：US08831131B2
公开(公告)日：2014-09-09
申请号：US13293008
申请日：2011-11-09
申请人： Marc Belleville
发明人： Marc Belleville
CPC分类号： G06F13/4286
摘要： The invention relates to the asynchronous communication of data in complex integrated systems, be it inside integrated circuit chips or between integrated circuit chips, for example in a compact stack of chips. According to the invention, the transmission is done on a single conductor of exchanges. The data are transmitted on this conductor in the form of at least three levels of potential, the first level representing a first value of data item transmitted, the second representing a second value of data item transmitted, and the third representing an inactive level. An acknowledgment signal is transmitted on the same exchange conductor as the data. This signal is preferably sent by the receiver in the form of the forcing of the exchange conductor by the receiver to the inactive potential level, the sender detecting this forcing.
摘要翻译： 本发明涉及复杂集成系统中的数据的异步通信，无论是在集成电路芯片内还是在集成电路芯片之间，例如在紧凑的芯片堆叠中。 根据本发明，传输是在单个交换机上进行的。 数据以至少三级电位的形式在该导体上发送，第一级表示所发送的数据项的第一值，第二级表示发送的数据项的第二值，第三级表示无效电平。 在与数据相同的交换导体上发送确认信号。 该信号优选地由接收机以接收机将交换导体强制为无效电平的形式发送，发送方检测到该强制。
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9.发明申请MEMORY CELLS IN DOUBLE-GATE CMOS TECHNOLOGY PROVIDED WITH TRANSISTORS WITH TWO INDEPENDENT GATES 失效具有两个独立门的晶体管的双栅极CMOS技术中的存储单元公开(公告)号：US20070211519A1
公开(公告)日：2007-09-13
申请号：US11683722
申请日：2007-03-08
申请人： Olivier THOMAS , Marc Belleville
发明人： Olivier THOMAS , Marc Belleville
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C11/412
摘要： This invention relates to an improved microelectronic RAM memory device, provided with 4T or 6T cells made using the double gate technology and each associated with two word lines.
摘要翻译： 本发明涉及一种改进的微电子RAM存储器件，其提供有使用双栅极技术制造的每个与两个字线相关联的4T或6T电池。
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公开(公告)号：US20060006913A1
公开(公告)日：2006-01-12
申请号：US10534462
申请日：2003-11-21
申请人： Daniel Chatroux , Marc Belleville
发明人： Daniel Chatroux , Marc Belleville
IPC分类号： H03L7/00
摘要： The integrated circuit comprises subassemblies connected in series enabling synchronization of the subassemblies to be achieved in simple manner. Each subassembly comprises a first and a second power supply terminal and a clock input. The subassemblies are connected in series to the terminals of a voltage supply source so that the same current flows through the different subassemblies. The clock input of each subassembly is connected to a common clock circuit by means of devices for shifting the clock signal levels, for example comprising capacitors and/or transistors. Each subassembly can comprise a decoupling capacitor and a voltage limiting circuit between its first and second power supply terminals.
摘要翻译： 集成电路包括串联连接的子组件，使得能够以简单的方式实现子组件的同步。 每个子组件包括第一和第二电源端子和时钟输入。 子组件串联连接到电压源的端子，使得相同的电流流过不同的子组件。 每个子组件的时钟输入通过用于移位时钟信号电平的装置（例如包括电容器和/或晶体管）连接到公共时钟电路。 每个子组件可以包括去耦电容器和在其第一和第二电源端子之间的电压限制电路。
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