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    In-situ ion implant activation and measurement apparatus
    4.
    发明授权
    In-situ ion implant activation and measurement apparatus 有权
    原位离子注入激活和测量装置

    公开(公告)号：US06417515B1

    公开(公告)日：2002-07-09

    申请号：US09527192

    申请日：2000-03-17

    申请人： Howard T. Barrett ,  John J. Ellis-Monaghan ,  Toshiharu Furukawa ,  James A. Slinkman

    发明人： Howard T. Barrett ,  John J. Ellis-Monaghan ,  Toshiharu Furukawa ,  James A. Slinkman

    IPC分类号： H01J37317

    CPC分类号： H01J37/3171 ,  H01J2237/30466 ,  H01J2237/31703

    摘要： A substrate, such as a semiconductor chip or wafer, is implanted along with product wafers in an ion implant vacuum system. The substrate is then annealed in an annealing step that is accomplished while the substrate is within the vacuum system. The annealer is a rapid thermal annealer, such as a laser annealer or a flash lamp annealer. The annealing step does not affect the product wafers. Then a measurement is performed on the implanted and annealed substrate while it is within the vacuum system that can be suitably correlated with implant dose. The measurement can be with a technique such as a four point probe or with a tool that measures optical reflectivity from a surface of the implanted substrate. An additional implant can then be provided to product wafers if necessary to come closer to the desired dose.

    摘要翻译： 将衬底（例如半导体芯片或晶片）与产品晶片一起植入离子注入真空系统中。 然后在基板处于真空系统内的退火步骤中退火基板。 退火炉是快速热退火炉，例如激光退火炉或闪光灯退火炉。 退火步骤不影响产品晶圆。 然后对植入和退火的基底进行测量，同时它在可以适当地与植入剂量相关联的真空系统内。 该测量可以采用诸如四点探针的技术或者用来测量从植入的衬底的表面的光学反射率的工具。 如果需要，可以将另外的植入物提供给产品晶片以更接近所需剂量。

    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE
    5.
    发明申请
    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE 有权
    用于减少谐波的硅绝缘体（SOI）结构和形成结构的方法

    公开(公告)号：US20110127529A1

    公开(公告)日：2011-06-02

    申请号：US12627343

    申请日：2009-11-30

    申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

    发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

    IPC分类号： H01L27/12 ,  H01L21/762

    CPC分类号： H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

    摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

    摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。

    Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method
    6.
    发明授权
    Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method 有权
    绝缘体上硅（SOI）结构配置为减少谐波，设计结构和方法

    公开(公告)号：US08698244B2

    公开(公告)日：2014-04-15

    申请号：US12634893

    申请日：2009-12-10

    申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

    发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

    IPC分类号： H01L27/12

    CPC分类号： H01L29/78603 ,  H01L21/84 ,  H01L27/1203

    摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

    摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 任选地，在该相同部分内形成微腔，以平衡电导率的任何增加和电阻率的相应增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于这种半导体结构的方法和设计结构的实施例。

    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD
    8.
    发明申请
    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD 有权
    用于减少谐波的硅绝缘体（SOI）结构，设计结构和方法

    公开(公告)号：US20110131542A1

    公开(公告)日：2011-06-02

    申请号：US12634893

    申请日：2009-12-10

    申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

    发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

    IPC分类号： G06F17/50

    CPC分类号： H01L29/78603 ,  H01L21/84 ,  H01L27/1203

    摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

    摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 任选地，在该相同部分内形成微腔，以平衡电导率的任何增加和电阻率的相应增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于这种半导体结构的方法和设计结构的实施例。