公开(公告)号：US06417070B1

公开(公告)日：2002-07-09

申请号：US09735988

申请日：2000-12-13

申请人： Arne W. Ballantine ,  Jeffrey S. Brown ,  Jeffrey D. Gilbert ,  James J. Quinlivan ,  James A. Slinkman ,  Anthony C. Speranza

发明人： Arne W. Ballantine ,  Jeffrey S. Brown ,  Jeffrey D. Gilbert ,  James J. Quinlivan ,  James A. Slinkman ,  Anthony C. Speranza

IPC分类号： H01L2176

CPC分类号： H01L21/76235 ,  H01L21/31662

摘要： A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.

摘要翻译： 通过快速热氧化获得包括具有在沟槽的顶部和底部具有圆角的衬垫的沟槽的结构。

公开(公告)号：US07714366B2

公开(公告)日：2010-05-11

申请号：US10904565

申请日：2004-11-16

申请人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

发明人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L21/28035 ,  H01L29/4925 ,  H01L29/665

摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.

摘要翻译： 通过在受控条件下沉积多晶硅来减少多晶硅栅电极中的多晶硅电耗，从而通过多晶硅的厚度来改变晶粒尺寸。 所得到的CMOS晶体管可以具有各自的晶粒尺寸的两个或更多个深度连续的区域，并且可以针对晶体尺寸的选择来最大化在栅极电介质附近的多晶硅中的掺杂剂活化，并且将多晶硅的电阻调整到高于该 第一区域并且远离栅极电介质。 多晶硅的区域可以具有作为从电介质膜的表面测量的距离的函数的变化的晶粒尺寸。

公开(公告)号：US06893948B2

公开(公告)日：2005-05-17

申请号：US10616962

申请日：2003-07-11

申请人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

发明人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/20 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28035 ,  H01L29/4925 ,  H01L29/665

摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

摘要翻译： 通过在受控条件下沉积多晶硅来减少多晶硅栅电极中的多晶硅电耗，从而通过多晶硅的厚度来改变晶粒尺寸。 所得到的结构可以具有两个或更多个相应晶粒尺寸的深度连续的区域，并且晶粒尺寸的选择被引导以最大限度地使栅极电介质附近的多晶硅中的掺杂剂活化最大化，并且将多晶硅的电阻定制在第一 区域并且远离栅极电介质。 该方法和所得结构有利地用于形成FET和掺杂多晶硅电阻器。

公开(公告)号：US06670263B2

公开(公告)日：2003-12-30

申请号：US09802702

申请日：2001-03-10

申请人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

发明人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

IPC分类号： H01L213205

CPC分类号： H01L21/28035 ,  H01L29/4925 ,  H01L29/665

摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

公开(公告)号：US06909157B2

公开(公告)日：2005-06-21

申请号：US10652307

申请日：2003-09-02

申请人： Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Steven M. Shank ,  Deborah A. Tucker ,  Beth A. Ward

发明人： Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Steven M. Shank ,  Deborah A. Tucker ,  Beth A. Ward

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L29/76

CPC分类号： H01L21/28202 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/518

摘要： Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.

公开(公告)号：US07138691B2

公开(公告)日：2006-11-21

申请号：US10707897

申请日：2004-01-22

申请人： Jay S. Burnham ,  John J. Ellis-Monaghan ,  James S. Nakos ,  James J. Quinlivan

发明人： Jay S. Burnham ,  John J. Ellis-Monaghan ,  James S. Nakos ,  James J. Quinlivan

IPC分类号： H01L29/76

CPC分类号： H01L21/823857

摘要： A semiconductor structure includes thin gate dielectrics that have been selectively nitrogen enriched. The amount of nitrogen introduced is sufficient to reduce or prevent gate leakage and dopant penetration, without appreciably degrading device performance. A lower concentration of nitrogen is introduced into pFET gate dielectrics than into nFET gate dielectrics. Nitridation may be accomplished selectively by various techniques, including rapid thermal nitridation (RTN), furnace nitridation, remote plasma nitridation (RPN), decoupled plasma nitridation (DPN), well implantation and/or polysilicon implantation.

摘要翻译： 半导体结构包括已经选择性地富氮的薄栅极电介质。 引入的氮气量足以减少或防止栅极泄漏和掺杂剂渗透，而不会明显降低器件性能。 较低浓度的氮被引入到pFET栅极电介质中，而不是nFET栅极电介质。 氮化可以通过各种技术选择性地完成，包括快速热氮化（RTN），炉氮化，远程等离子体氮化（RPN），去耦等离子体氮化（DPN），阱注入和/或多晶硅注入。

公开(公告)号：US06967167B2

公开(公告)日：2005-11-22

申请号：US10605435

申请日：2003-09-30

申请人： Peter J. Geiss ,  Alvin J. Joseph ,  Xuefeng Liu ,  James S. Nakos ,  James J. Quinlivan

发明人： Peter J. Geiss ,  Alvin J. Joseph ,  Xuefeng Liu ,  James S. Nakos ,  James J. Quinlivan

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/331 ,  H01L21/461

CPC分类号： H01L29/66242 ,  H01L21/31116

摘要： A method for removing silicon dioxide residuals is disclosed. The method includes reacting a portion of a silicon dioxide layer (i.e., oxide) to form a reaction product layer, removing the reaction product layer and annealing in an environment to remove oxide residuals. The method finds application in a variety of semiconductor fabrication processes including, for example, fabrication of a vertical HBT or silicon-to-silicon interface without an oxide interface.

摘要翻译： 公开了一种去除二氧化硅残留物的方法。 该方法包括使一部分二氧化硅层（即氧化物）反应以形成反应产物层，除去反应产物层并在环境中退火以除去氧化物残余物。 该方法应用于各种半导体制造工艺中，包括例如制造垂直HBT或无硅氧化物界面的硅 - 硅界面。

公开(公告)号：US08709887B2

公开(公告)日：2014-04-29

申请号：US11778238

申请日：2007-07-16

申请人： Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Bernie Roque, Jr. ,  Steven M. Shank ,  Beth A. Ward

发明人： Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Bernie Roque, Jr. ,  Steven M. Shank ,  Beth A. Ward

IPC分类号： H01L21/336

CPC分类号： H01L21/28202 ,  H01L21/28035 ,  H01L21/3144 ,  H01L29/518

摘要： A method of fabricating a gate dielectric layer. The method includes: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.

摘要翻译： 一种制造栅极电介质层的方法。 该方法包括：提供衬底; 在所述基板的顶表面上形成二氧化硅层; 在还原气氛中进行等离子体氮化，将二氧化硅层转换成氮氧化硅层。 如此形成的电介质层可用于制造MOSFET。

公开(公告)号：US06706644B2

公开(公告)日：2004-03-16

申请号：US10206427

申请日：2002-07-26

申请人： Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Steven M. Shank ,  Deborah A. Tucker ,  Beth A. Ward

发明人： Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Steven M. Shank ,  Deborah A. Tucker ,  Beth A. Ward

IPC分类号： H01L2131

CPC分类号： H01L21/28202 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/518

摘要： Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.

摘要翻译： 使用诸如远程等离子体氮化（RPN）的方法将氮气引入栅极介电层。 然而，这些方法产生氮化层，其中层的横截面轮廓和氮分布都不均匀。 使氮化层进行额外的NO退火工艺增加了氮化层的均匀性。

公开(公告)号：US07291568B2

公开(公告)日：2007-11-06

申请号：US10604905

申请日：2003-08-26

申请人： Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Bernie A. Roque, Jr. ,  Steven M. Shank ,  Beth A. Ward

发明人： Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Bernie A. Roque, Jr. ,  Steven M. Shank ,  Beth A. Ward

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28202 ,  H01L21/28035 ,  H01L21/3144 ,  H01L29/518

摘要： A method of fabricating a gate dielectric layer, including: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.

摘要翻译： 一种制造栅极电介质层的方法，包括：提供衬底; 在所述基板的顶表面上形成二氧化硅层; 在还原气氛中进行等离子体氮化，将二氧化硅层转换成氮氧化硅层。 如此形成的电介质层可用于制造MOSFET。