公开(公告)号：US06417515B1

公开(公告)日：2002-07-09

申请号：US09527192

申请日：2000-03-17

申请人： Howard T. Barrett ,  John J. Ellis-Monaghan ,  Toshiharu Furukawa ,  James A. Slinkman

发明人： Howard T. Barrett ,  John J. Ellis-Monaghan ,  Toshiharu Furukawa ,  James A. Slinkman

IPC分类号： H01J37317

CPC分类号： H01J37/3171 ,  H01J2237/30466 ,  H01J2237/31703

摘要： A substrate, such as a semiconductor chip or wafer, is implanted along with product wafers in an ion implant vacuum system. The substrate is then annealed in an annealing step that is accomplished while the substrate is within the vacuum system. The annealer is a rapid thermal annealer, such as a laser annealer or a flash lamp annealer. The annealing step does not affect the product wafers. Then a measurement is performed on the implanted and annealed substrate while it is within the vacuum system that can be suitably correlated with implant dose. The measurement can be with a technique such as a four point probe or with a tool that measures optical reflectivity from a surface of the implanted substrate. An additional implant can then be provided to product wafers if necessary to come closer to the desired dose.

摘要翻译： 将衬底（例如半导体芯片或晶片）与产品晶片一起植入离子注入真空系统中。 然后在基板处于真空系统内的退火步骤中退火基板。 退火炉是快速热退火炉，例如激光退火炉或闪光灯退火炉。 退火步骤不影响产品晶圆。 然后对植入和退火的基底进行测量，同时它在可以适当地与植入剂量相关联的真空系统内。 该测量可以采用诸如四点探针的技术或者用来测量从植入的衬底的表面的光学反射率的工具。 如果需要，可以将另外的植入物提供给产品晶片以更接近所需剂量。

公开(公告)号：US06274465B1

公开(公告)日：2001-08-14

申请号：US09538309

申请日：2000-03-30

申请人： Arne W. Ballantine ,  John J. Ellis-Monaghan ,  Toshiharu Furukawa ,  Glenn R. Miller ,  James A. Slinkman

发明人： Arne W. Ballantine ,  John J. Ellis-Monaghan ,  Toshiharu Furukawa ,  Glenn R. Miller ,  James A. Slinkman

IPC分类号： H01L2104

CPC分类号： H01L21/324 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/326

摘要： A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to a DC electric field.

摘要翻译： 一种用于在半导体器件中形成期望的接合剖面的方法。 将至少一种掺杂剂引入到半导体衬底中。 所述至少一种掺杂剂通过半导体衬底和所述至少一种掺杂剂退火而在半导体衬底中扩散，同时将半导体衬底暴露于DC电场。

公开(公告)号：US06552411B2

公开(公告)日：2003-04-22

申请号：US09809887

申请日：2001-03-16

申请人： Arne W. Ballantine ,  John J. Ellis-Monaghan ,  Toshihura Furukawa ,  Jeffrey D. Gilbert ,  Glenn R. Miller ,  James A. Slinkman

发明人： Arne W. Ballantine ,  John J. Ellis-Monaghan ,  Toshihura Furukawa ,  Jeffrey D. Gilbert ,  Glenn R. Miller ,  James A. Slinkman

IPC分类号： H01L2900

CPC分类号： H01L21/324 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/326

摘要： A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

摘要翻译： 一种用于在半导体器件中形成期望的接合剖面的方法。 将至少一种掺杂剂引入到半导体衬底中。 所述至少一种掺杂剂通过对所述半导体衬底和所述至少一种掺杂物退火而在所述半导体衬底中扩散，同时将所述半导体衬底暴露于电场。

公开(公告)号：US08698244B2

公开(公告)日：2014-04-15

申请号：US12634893

申请日：2009-12-10

申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L27/12

CPC分类号： H01L29/78603 ,  H01L21/84 ,  H01L27/1203

摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 任选地，在该相同部分内形成微腔，以平衡电导率的任何增加和电阻率的相应增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于这种半导体结构的方法和设计结构的实施例。

公开(公告)号：US08471340B2

公开(公告)日：2013-06-25

申请号：US12627343

申请日：2009-11-30

申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L21/70

CPC分类号： H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

公开(公告)号：US20110131542A1

公开(公告)日：2011-06-02

申请号：US12634893

申请日：2009-12-10

申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： G06F17/50

CPC分类号： H01L29/78603 ,  H01L21/84 ,  H01L27/1203

摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 任选地，在该相同部分内形成微腔，以平衡电导率的任何增加和电阻率的相应增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于这种半导体结构的方法和设计结构的实施例。

公开(公告)号：US06822311B2

公开(公告)日：2004-11-23

申请号：US10413301

申请日：2003-04-15

申请人： Arne W. Ballantine ,  John J. Ellis-Monaghan ,  Toshihura Furukawa ,  Jeffrey D. Gilbert ,  Glenn R. Miller ,  James A. Slinkman

发明人： Arne W. Ballantine ,  John J. Ellis-Monaghan ,  Toshihura Furukawa ,  Jeffrey D. Gilbert ,  Glenn R. Miller ,  James A. Slinkman

IPC分类号： H01L2900

CPC分类号： H01L21/2253 ,  C21D1/04 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/326

摘要： A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

摘要翻译： 一种用于在半导体器件中形成期望的接合剖面的方法。 将至少一种掺杂剂引入到半导体衬底中。 所述至少一种掺杂剂通过对所述半导体衬底和所述至少一种掺杂物退火而在所述半导体衬底中扩散，同时将所述半导体衬底暴露于电场。

公开(公告)号：US20110127529A1

公开(公告)日：2011-06-02

申请号：US12627343

申请日：2009-11-30

申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。

公开(公告)号：US08927357B2

公开(公告)日：2015-01-06

申请号：US13294731

申请日：2011-11-11

申请人： Kevin K. Chan ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

发明人： Kevin K. Chan ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC分类号： H01L21/337 ,  H01L29/10 ,  H01L27/06 ,  H01L29/66 ,  H01L29/737 ,  H01L29/808 ,  H01L29/165 ,  H01L29/08

CPC分类号： H01L29/8086 ,  G06F17/5045 ,  H01L27/0623 ,  H01L29/0817 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1058 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/808

摘要： Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.

摘要翻译： 结型场效应晶体管，用于制造结型场效应晶体管的方法，以及结型场效应晶体管的设计结构。 结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。 形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。 源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

公开(公告)号：US08890557B2

公开(公告)日：2014-11-18

申请号：US13443450

申请日：2012-04-10

申请人： Yoba Amoah ,  John J. Ellis-Monaghan ,  Roger C. Kuo ,  Molly J. Leitch ,  Zhihong Zhang

发明人： Yoba Amoah ,  John J. Ellis-Monaghan ,  Roger C. Kuo ,  Molly J. Leitch ,  Zhihong Zhang

IPC分类号： G01R31/3187

CPC分类号： G01R31/318511 ,  G01R31/2856 ,  G11C29/006 ,  G11C29/12 ,  G11C2029/1206

摘要： A method of testing a semiconductor wafer and a related structure. In various embodiments, a method includes: placing a probe on a first chip on the semiconductor wafer; testing a scribe line automatic built-in self-test (ABIST) for the first chip to search for a fault; progressively testing a subsequent scribe line ABIST for a subsequent chip on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault; moving the probe point to the subsequent chip and retesting the subsequent scribe line ABIST in response to determining the ABIST for the subsequent chip indicates a fault; and testing a further subsequent scribe line ABIST for a further subsequent chip on the semiconductor wafer in response to determining the retesting of the subsequent scribiline ABIST does not indicate a fault in the subsequent scribe line ABIST.

摘要翻译： 一种半导体晶片的测试方法及相关结构。 在各种实施例中，一种方法包括：将探针放置在半导体晶片上的第一芯片上; 测试划线自动内置自检（ABIST）为第一芯片寻找故障; 响应于确定第一芯片的ABIST而对半导体晶片上的后续芯片进行随后的划线ABIST的逐步测试不表示故障; 将探针点移动到随后的芯片，并且响应于确定随后芯片的ABIST指示故障，重新测试随后的划线ABIST; 以及响应于确定随后的scribiline的重新测试，测试另一后续划线ABIST用于半导体晶片上的另外的后续芯片，ABIST不指示后续划线ABIST中的故障。