公开(公告)号：US08853550B2

公开(公告)日：2014-10-07

申请号：US13035127

申请日：2011-02-25

申请人： Arun Virupaksha Gowda ,  Kevin Matthew Durocher ,  James Wilson Rose ,  Paul Jeffrey Gillespie ,  Richard Alfred Beaupre ,  David Richard Esler

发明人： Arun Virupaksha Gowda ,  Kevin Matthew Durocher ,  James Wilson Rose ,  Paul Jeffrey Gillespie ,  Richard Alfred Beaupre ,  David Richard Esler

IPC分类号： H05K1/03 ,  H05K3/34 ,  B23K35/30 ,  B23K35/36 ,  B23K35/38 ,  B23K35/28 ,  B23K35/32 ,  B23K3/06 ,  H05K3/24 ,  H05K3/00

CPC分类号： B23K3/06 ,  B23K35/286 ,  B23K35/308 ,  B23K35/325 ,  B23K35/3606 ,  B23K35/38 ,  H05K3/0061 ,  H05K3/244 ,  H05K3/3452 ,  H05K2201/2081

摘要： A circuit board includes a solder wettable surface and a metal mask configured to restrict solder from flowing outside the solder wettable surface of the circuit board.

摘要翻译： 电路板包括焊料可润湿表面和金属掩模，金属掩模被配置为限制焊料流动到电路板的可焊接润湿表面之外。

公开(公告)号：US07919714B2

公开(公告)日：2011-04-05

申请号：US11746260

申请日：2007-05-09

申请人： Arun Virupaksha Gowda ,  Kevin Matthew Durocher ,  James Wilson Rose ,  Paul Jeffrey Gillespie ,  Richard Alfred Beaupre ,  David Richard Esler

发明人： Arun Virupaksha Gowda ,  Kevin Matthew Durocher ,  James Wilson Rose ,  Paul Jeffrey Gillespie ,  Richard Alfred Beaupre ,  David Richard Esler

IPC分类号： H05K1/00

CPC分类号： B23K3/06 ,  B23K35/286 ,  B23K35/308 ,  B23K35/325 ,  B23K35/3606 ,  B23K35/38 ,  H05K3/0061 ,  H05K3/244 ,  H05K3/3452 ,  H05K2201/2081

摘要： An assembly including a solder wettable surface is provided. The assembly also includes a metal mask configured to restrict solder from flowing outside the solder wettable surface.

摘要翻译： 提供了一种包括焊料润湿表面的组件。 组件还包括配置为限制焊料流过焊料可润湿表面的金属掩模。

公开(公告)号：US20110139495A1

公开(公告)日：2011-06-16

申请号：US13035127

申请日：2011-02-25

申请人： Arun Virupaksha Gowda ,  Kevin Matthew Durocher ,  James Wilson Rose ,  Paul Jeffrey Gillespie ,  Richard Alfred Beaupre ,  David Richard Esler

发明人： Arun Virupaksha Gowda ,  Kevin Matthew Durocher ,  James Wilson Rose ,  Paul Jeffrey Gillespie ,  Richard Alfred Beaupre ,  David Richard Esler

IPC分类号： H05K1/03

CPC分类号： B23K3/06 ,  B23K35/286 ,  B23K35/308 ,  B23K35/325 ,  B23K35/3606 ,  B23K35/38 ,  H05K3/0061 ,  H05K3/244 ,  H05K3/3452 ,  H05K2201/2081

摘要： A circuit board includes a solder wettable surface and a metal mask configured to restrict solder from flowing outside the solder wettable surface of the circuit board.

摘要翻译： 电路板包括焊料可润湿表面和金属掩模，金属掩模被配置为限制焊料流动到电路板的可焊接润湿表面之外。

公开(公告)号：US20120146234A1

公开(公告)日：2012-06-14

申请号：US12962761

申请日：2010-12-08

申请人： Richard Alfred Beaupre ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda ,  Thomas Bert Gorczyca

发明人： Richard Alfred Beaupre ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda ,  Thomas Bert Gorczyca

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/3171 ,  H01L21/56 ,  H01L23/3164 ,  H01L23/3192 ,  H01L24/19 ,  H01L24/20 ,  H01L29/0657 ,  H01L2224/24 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24227 ,  H01L2224/76155 ,  H01L2224/82 ,  H01L2224/82102 ,  H01L2224/82105 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/12036 ,  H01L2924/1204 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/00

摘要： A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.

公开(公告)号：US08487416B2

公开(公告)日：2013-07-16

申请号：US13247216

申请日：2011-09-28

申请人： Eladio Clemente Delgado ,  Arun Virupaksha Gowda ,  Antonio Caiafa ,  Brian Lynn Rowden ,  Ljubisa Dragoljub Stevanovic ,  Richard Alfred Beaupre

发明人： Eladio Clemente Delgado ,  Arun Virupaksha Gowda ,  Antonio Caiafa ,  Brian Lynn Rowden ,  Ljubisa Dragoljub Stevanovic ,  Richard Alfred Beaupre

IPC分类号： H01L23/552 ,  H01L23/34 ,  H01L23/04 ,  H01L23/12 ,  H05K7/20 ,  H05K9/00

CPC分类号： H01L23/552 ,  H01L25/117 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power module includes at least one semiconductor die holding structure. Each die holding structure has a substantially cylindrical outer profile and a central axis. Each die holding structure is disposed within a common cylindrical EMI shield. A plurality of semiconductor devices are mounted to each die holding structure to form a substantially symmetric die mounting pattern respect to the central axis of the die holding structure.

摘要翻译： 电源模块包括至少一个半导体管芯保持结构。 每个模具保持结构具有基本上圆柱形的外部轮廓和中心轴线。 每个管芯保持结构设置在共同的圆柱形EMI屏蔽内。 多个半导体器件被安装到每个管芯保持结构，以相对于管芯保持结构的中心轴线形成大致对称的管芯安装图案。

公开(公告)号：US20120329207A1

公开(公告)日：2012-12-27

申请号：US13606186

申请日：2012-09-07

申请人： Richard Alfred Beaupre ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda ,  Thomas Bert Gorczyca

发明人： Richard Alfred Beaupre ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda ,  Thomas Bert Gorczyca

IPC分类号： H01L21/768 ,  H01L31/18 ,  H01L21/56

CPC分类号： H01L23/3171 ,  H01L21/56 ,  H01L23/3164 ,  H01L23/3192 ,  H01L24/19 ,  H01L24/20 ,  H01L29/0657 ,  H01L2224/24 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24227 ,  H01L2224/76155 ,  H01L2224/82 ,  H01L2224/82102 ,  H01L2224/82105 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/12036 ,  H01L2924/1204 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/00

摘要： A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.

摘要翻译： 半导体器件封装包括其上形成有连接焊盘的半导体器件，其中连接焊盘形成在半导体器件的第一和第二表面上，半导体器件的边缘在其间延伸。 在半导体器件上施加第一钝化层，并且将基底电介质层压体固定到半导体器件的第一表面，其厚度大于第一钝化层的厚度。 具有大于第一钝化层的厚度的第二钝化层施加在第一钝化层和半导体器件上以覆盖半导体器件的第二表面和边缘，并且金属互连件连接到连接焊盘， 所述金属互连件延伸穿过通过所述第一和第二钝化层和所述基底电介质层压片形成的通孔，以形成与所述连接焊盘的连接。

公开(公告)号：US20100038774A1

公开(公告)日：2010-02-18

申请号：US12193429

申请日：2008-08-18

申请人： Richard S. Zhang ,  Richard Alfred Beaupre ,  Ramakrishna Venkata Mallina ,  Arun Virupaksha Gowda ,  Le Yan ,  Ljubisa Dragoljub Stevanovic ,  Peter Morley ,  Stephen Adam Solovitz

发明人： Richard S. Zhang ,  Richard Alfred Beaupre ,  Ramakrishna Venkata Mallina ,  Arun Virupaksha Gowda ,  Le Yan ,  Ljubisa Dragoljub Stevanovic ,  Peter Morley ,  Stephen Adam Solovitz

IPC分类号： H01L23/34

CPC分类号： H01L23/473 ,  H01L24/72 ,  H01L2924/01079 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/3011 ,  H01L2924/00

摘要： A heat sink for cooling at least one electronic device package is provided. The electronic device package has an upper contact surface and a lower contact surface. The heat sink comprises at least one thermally conductive material and defines multiple inlet manifolds configured to receive a coolant, multiple outlet manifolds configured to exhaust the coolant, and multiple millichannels configured to receive the coolant from the inlet manifolds and to deliver the coolant to the outlet manifolds. The manifolds and millichannels are disposed proximate to the respective one of the upper and lower contact surface of the electronic device package for cooling the respective surface with the coolant.

摘要翻译： 提供了用于冷却至少一个电子设备封装的散热器。 电子器件封装具有上接触表面和下接触表面。 散热器包括至少一个导热材料并且限定被配置为接收冷却剂的多个入口歧管，被配置为排出冷却剂的多个出口歧管以及被配置成从进气歧管接收冷却剂并将冷却剂输送到出口的多个通路 歧管。 歧管和毫通道靠近电子装置包装的上接触表面和下接触表面中的相应一个设置，用于用冷却剂冷却相应的表面。

公开(公告)号：US20130075878A1

公开(公告)日：2013-03-28

申请号：US13247216

申请日：2011-09-28

申请人： Eladio Clemente Delgado ,  Arun Virupaksha Gowda ,  Antonio Caiafa ,  Brian Lynn Rowden ,  Ljubisa Dragoljub Stevanovic ,  Richard Alfred Beaupre

发明人： Eladio Clemente Delgado ,  Arun Virupaksha Gowda ,  Antonio Caiafa ,  Brian Lynn Rowden ,  Ljubisa Dragoljub Stevanovic ,  Richard Alfred Beaupre

IPC分类号： H01L23/552

CPC分类号： H01L23/552 ,  H01L25/117 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power module includes at least one semiconductor die holding structure. Each die holding structure has a substantially cylindrical outer profile and a central axis. Each die holding structure is disposed within a common cylindrical EMI shield. A plurality of semiconductor devices are mounted to each die holding structure to form a substantially symmetric die mounting pattern respect to the central axis of the die holding structure.

摘要翻译： 电源模块包括至少一个半导体管芯保持结构。 每个模具保持结构具有基本上圆柱形的外部轮廓和中心轴线。 每个管芯保持结构设置在共同的圆柱形EMI屏蔽内。 多个半导体器件被安装到每个管芯保持结构，以相对于管芯保持结构的中心轴线形成大致对称的管芯安装图案。

公开(公告)号：US08310040B2

公开(公告)日：2012-11-13

申请号：US12962761

申请日：2010-12-08

申请人： Richard Alfred Beaupre ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda ,  Thomas Bert Gorczyca

发明人： Richard Alfred Beaupre ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda ,  Thomas Bert Gorczyca

IPC分类号： H01L23/48

CPC分类号： H01L23/3171 ,  H01L21/56 ,  H01L23/3164 ,  H01L23/3192 ,  H01L24/19 ,  H01L24/20 ,  H01L29/0657 ,  H01L2224/24 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24227 ,  H01L2224/76155 ,  H01L2224/82 ,  H01L2224/82102 ,  H01L2224/82105 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/12036 ,  H01L2924/1204 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/00

摘要： A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.

摘要翻译： 半导体器件封装包括其上形成有连接焊盘的半导体器件，其中连接焊盘形成在半导体器件的第一和第二表面上，半导体器件的边缘在其间延伸。 在半导体器件上施加第一钝化层，并且将基底电介质层压体固定到半导体器件的第一表面，其厚度大于第一钝化层的厚度。 具有大于第一钝化层的厚度的第二钝化层施加在第一钝化层和半导体器件上以覆盖半导体器件的第二表面和边缘，并且金属互连件连接到连接焊盘， 所述金属互连件延伸穿过通过所述第一和第二钝化层和所述基底电介质层压片形成的通孔，以形成与所述连接焊盘的连接。

公开(公告)号：US20100230800A1

公开(公告)日：2010-09-16

申请号：US12404272

申请日：2009-03-13

申请人： Richard Alfred Beaupre ,  Arun Virupaksha Gowda ,  Ljubisa Dragol jub Stevanovic ,  Stephen Adam Solovitz

发明人： Richard Alfred Beaupre ,  Arun Virupaksha Gowda ,  Ljubisa Dragol jub Stevanovic ,  Stephen Adam Solovitz

IPC分类号： H01L23/52

CPC分类号： H01L23/3735 ,  H01L23/051 ,  H01L23/42 ,  H01L23/473 ,  H01L24/24 ,  H01L25/072 ,  H01L2224/24137 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/14

摘要： A power module includes one or more semiconductor power devices having a power overlay (POL) bonded thereto. A first heat sink is bonded to the semiconductor power devices on a side opposite the POL. A second heat sink is bonded to the POL opposite the side of the POL bonded to the semiconductor power devices. The semiconductor power devices, POL, first channel heat sink, and second channel heat sink together form a double side cooled power overlay module. The second channel heat sink is bonded to the POL solely via a compliant thermal interface material without the need for planarizing, brazing or metallurgical bonding.

摘要翻译： 功率模块包括具有与其结合的功率覆盖（POL）的一个或多个半导体功率器件。 第一散热器在与POL相对的一侧结合到半导体功率器件。 第二散热器接合到与结合到半导体功率器件的POL的侧面相反的POL。 半导体功率器件POL，第一通道散热器和第二通道散热器一起形成双侧冷却功率覆盖模块。 第二通道散热器仅通过柔性热界面材料结合到POL，而不需要平坦化，钎焊或冶金结合。