公开(公告)号：US20120038051A1

公开(公告)日：2012-02-16

申请号：US13281491

申请日：2011-10-26

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US07786003B1

公开(公告)日：2010-08-31

申请号：US11136569

申请日：2005-05-25

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

IPC分类号： H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US08368219B2

公开(公告)日：2013-02-05

申请号：US13281491

申请日：2011-10-26

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jusuke Ogura

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US08049334B1

公开(公告)日：2011-11-01

申请号：US12843131

申请日：2010-07-26

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jusuke Ogura

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US06828199B2

公开(公告)日：2004-12-07

申请号：US10022798

申请日：2001-12-20

申请人： Jusuke Ogura ,  Mark T. Ramsbey ,  Arvind Halliyal ,  Zoran Krivokapic ,  Minh Van Ngo ,  Nicholas H. Tripisas

发明人： Jusuke Ogura ,  Mark T. Ramsbey ,  Arvind Halliyal ,  Zoran Krivokapic ,  Minh Van Ngo ,  Nicholas H. Tripisas

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L21/743 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

摘要： A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide is formed on top of the metal silicide. A word line is formed over the ONO layer and the bit line oxide, and a low resistance silicide is provided on top of the word line. The silicide is formed by laser thermal annealing, for example.

摘要翻译： 用于制造该器件的MONOS器件和方法具有形成在衬底上的电荷捕获介电层，例如氧化物 - 氮化物 - 氧化物（ONO）层。 通过ONO层和衬底产生凹陷。 在凹部中形成金属硅化物位线，并且在金属硅化物的顶部上形成位线氧化物。 在ONO层和位线氧化物之间形成字线，并且在字线的顶部提供低电阻硅化物。 硅化物例如由激光热退火形成。

公开(公告)号：US06617215B1

公开(公告)日：2003-09-09

申请号：US10109235

申请日：2002-03-27

申请人： Arvind Halliyal ,  Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Angela T. Hui ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Angela T. Hui ,  Jusuke Ogura

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L21/0332 ,  H01L21/32139 ,  H01L27/115

摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.

摘要翻译： 用于MirrorBit（R）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质材料。 植入第一和第二位线，并存放字线材料。 硬掩模材料沉积在字线材料上。 硬掩模材料是具有沉积而不是生长的特征的材料。 光致抗蚀剂材料沉积在字线材料上并被图案化以形成图案化的硬掩模。 去除图案化的光致抗蚀剂材料。 使用图案化的硬掩模处理字线材料以形成字线。 去除图案化的硬掩模材料。

公开(公告)号：US06548855B1

公开(公告)日：2003-04-15

申请号：US10147622

申请日：2002-05-16

申请人： Mark T. Ramsbey ,  Arvind Halliyal ,  Kuo-Tung Chang ,  Nicholas H. Tripsas ,  Wei Zheng ,  Unsoon Kim

发明人： Mark T. Ramsbey ,  Arvind Halliyal ,  Kuo-Tung Chang ,  Nicholas H. Tripsas ,  Wei Zheng ,  Unsoon Kim

IPC分类号： H01L2976

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11539

摘要： A non-volatile memory device for retention of data when electrical power is terminated. The non-volatile memory device includes at least one memory cell and a charge pump for stepping up the incoming voltage supply. The charge pump includes at least one capacitor, wherein the dielectric of the charge pump capacitor and the dielectric of the memory cell are formed during the same processing step.

摘要翻译： 一种用于在电力终止时保留数据的非易失性存储器件。 非易失性存储器件包括至少一个存储单元和用于加速输入电压源的电荷泵。 电荷泵包括至少一个电容器，其中电荷泵电容器的电介质和存储单元的电介质在相同的处理步骤期间形成。

公开(公告)号：US06884681B1

公开(公告)日：2005-04-26

申请号：US10672093

申请日：2003-09-26

申请人： Tazrien Kamal ,  Arvind Halliyal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Rinji Sugino

发明人： Tazrien Kamal ,  Arvind Halliyal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Rinji Sugino

IPC分类号： H01L21/336 ,  H01L21/8246

CPC分类号： H01L27/11568 ,  H01L29/66833

摘要： A method for manufacturing a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.

摘要翻译： 一种用于制造MirrorBit（闪存）闪存的方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。 植入第一和第二位线，并在完成内存之前形成字线。 在字线之间形成间隔，并且在字线之间形成层间电介质层。 第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。

公开(公告)号：US07670936B1

公开(公告)日：2010-03-02

申请号：US10273184

申请日：2002-10-18

申请人： Arvind Halliyal ,  Nicholas H. Tripsas ,  Mark T. Ramsbey

发明人： Arvind Halliyal ,  Nicholas H. Tripsas ,  Mark T. Ramsbey

IPC分类号： H01L21/425

CPC分类号： H01L21/268 ,  H01L21/02057 ,  H01L21/28202 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device includes forming an interface layer, a nitrided gate dielectric, a gate electrode, and source drain regions. The interface layer is formed in a substrate by laser processing. The nitrided gate dielectric is formed over the interface layer by laser processing. The gate electrode is formed over the substrate and the gate dielectric after the laser processing step, and source/drain regions are formed in the substrate proximate to the gate electrode.

摘要翻译： 制造半导体器件的方法包括形成界面层，氮化栅极电介质，栅电极和源漏区。 界面层通过激光加工形成在基板中。 通过激光加工在界面层上形成氮化栅极电介质。 在激光加工步骤之后，栅极电极形成在衬底和栅极电介质上，并且源极/漏极区域形成在靠近栅电极的衬底中。

公开(公告)号：US06861307B2

公开(公告)日：2005-03-01

申请号：US10631199

申请日：2003-07-31

申请人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

发明人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/792 ,  H01L21/8238

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7923

摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

摘要翻译： 在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。 该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层 势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。 去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。