公开(公告)号：US08368219B2

公开(公告)日：2013-02-05

申请号：US13281491

申请日：2011-10-26

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jusuke Ogura

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US08049334B1

公开(公告)日：2011-11-01

申请号：US12843131

申请日：2010-07-26

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jusuke Ogura

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US20120038051A1

公开(公告)日：2012-02-16

申请号：US13281491

申请日：2011-10-26

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US07786003B1

公开(公告)日：2010-08-31

申请号：US11136569

申请日：2005-05-25

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

IPC分类号： H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US06828199B2

公开(公告)日：2004-12-07

申请号：US10022798

申请日：2001-12-20

申请人： Jusuke Ogura ,  Mark T. Ramsbey ,  Arvind Halliyal ,  Zoran Krivokapic ,  Minh Van Ngo ,  Nicholas H. Tripisas

发明人： Jusuke Ogura ,  Mark T. Ramsbey ,  Arvind Halliyal ,  Zoran Krivokapic ,  Minh Van Ngo ,  Nicholas H. Tripisas

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L21/743 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

摘要： A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide is formed on top of the metal silicide. A word line is formed over the ONO layer and the bit line oxide, and a low resistance silicide is provided on top of the word line. The silicide is formed by laser thermal annealing, for example.

摘要翻译： 用于制造该器件的MONOS器件和方法具有形成在衬底上的电荷捕获介电层，例如氧化物 - 氮化物 - 氧化物（ONO）层。 通过ONO层和衬底产生凹陷。 在凹部中形成金属硅化物位线，并且在金属硅化物的顶部上形成位线氧化物。 在ONO层和位线氧化物之间形成字线，并且在字线的顶部提供低电阻硅化物。 硅化物例如由激光热退火形成。

公开(公告)号：US06861307B2

公开(公告)日：2005-03-01

申请号：US10631199

申请日：2003-07-31

申请人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

发明人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/792 ,  H01L21/8238

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7923

摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

摘要翻译： 在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。 该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层 势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。 去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。

公开(公告)号：US07001807B1

公开(公告)日：2006-02-21

申请号：US10997345

申请日：2004-11-24

申请人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

发明人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

IPC分类号： H01L21/31

CPC分类号： H01L29/513 ,  H01L21/28282 ,  H01L29/512 ,  H01L29/517 ,  H01L29/7923

摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

公开(公告)号：US06639271B1

公开(公告)日：2003-10-28

申请号：US10027253

申请日：2001-12-20

申请人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

发明人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

IPC分类号： H01L29792

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7923

摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

摘要翻译： 在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。 该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层 势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。 去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。

公开(公告)号：US07029958B2

公开(公告)日：2006-04-18

申请号：US10699887

申请日：2003-11-04

申请人： Cyrus E. Tabery ,  Shibly S. Ahmed ,  Matthew S. Buynoski ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang ,  Chih-Yuh Yang ,  Bin Yu

发明人： Cyrus E. Tabery ,  Shibly S. Ahmed ,  Matthew S. Buynoski ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang ,  Chih-Yuh Yang ,  Bin Yu

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7842

摘要： A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.

摘要翻译： 一种形成金属氧化物半导体场效应晶体管（MOSFET）的方法包括在衬底上构图翅片区域，源极区域和漏极区域，在翅片区域中形成鳍片，并在鳍片区域中形成掩模 。 该方法还包括蚀刻掩模以暴露MOSFET的沟道区域，蚀刻鳍以在沟道区域中减薄翅片的宽度，在鳍上方形成栅极，以及形成与栅极，源区和 漏极区域。

公开(公告)号：US06765303B1

公开(公告)日：2004-07-20

申请号：US10429697

申请日：2003-05-06

申请人： Zoran Krivokapic ,  Judy Xilin An ,  Matthew S. Buynoski

发明人： Zoran Krivokapic ,  Judy Xilin An ,  Matthew S. Buynoski

IPC分类号： H01L2711

CPC分类号： B82Y10/00 ,  G11C11/412 ,  H01L27/11 ,  H01L29/66818 ,  H01L29/785 ,  Y10S257/903

摘要： A SRAM cell includes a single FinFET and two resonant tunnel diodes. The FinFet has multiple channel regions formed from separate fins. The resonant tunnel diodes may be formed from FinFET type fins. In particular, the resonant diodes may includes a thin, undoped silicon region surrounded by a dielectric. The SRAM cell is small and provides fast read/write access times.

摘要翻译： SRAM单元包括单个FinFET和两个谐振隧道二极管。 FinFet具有由独立翅片形成的多个通道区域。 谐振隧道二极管可以由FinFET型鳍形成。 特别地，谐振二极管可以包括由电介质围绕的薄的未掺杂的硅区域。 SRAM单元很小，并提供快速的读/写访问时间。