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公开(公告)号：US20070228486A1
公开(公告)日：2007-10-04
申请号：US11761288
申请日：2007-06-11
IPC分类号： H01L29/768
CPC分类号： H01L29/4908 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/4975 , H01L29/517 , H01L29/66643 , H01L29/785
摘要： A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a first gate electrode formed on the first gate insulator and including a compound of a metal M and a first group-IV elements Si1-a Gea (0≦a≦1), the p-type device including a p-channel region formed on the substrate, p-type source and drain regions formed opposite to each other interposing the p-channel region therebetween, a second gate insulator formed on the p-channel region, and a second gate electrode formed on the second gate insulator, and including a compound of the metal M and a second group-IV element Si1-c Gec (0≦c≦1, a≠c).
摘要翻译： 半导体器件包括形成在衬底上的n型和p型半导体器件，n型器件包括形成在衬底上的n沟道区，n型源极和漏极区彼此相对形成， 沟道区域，形成在n沟道区上的第一栅极绝缘体和形成在第一栅极绝缘体上的第一栅电极，并且包括金属M和第一族IV元素Si 1-a的化合物， （0 <= a <= 1），p型器件包括形成在衬底上的p沟道区域，彼此相对形成的p型源极和漏极区域 在其间插入p沟道区域，形成在p沟道区域上的第二栅极绝缘体和形成在第二栅极绝缘体上的第二栅电极，并且包括金属M和第二IV族元素Si c）。
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公开(公告)号：US07456096B2
公开(公告)日：2008-11-25
申请号：US11530724
申请日：2006-09-11
申请人： Takashi Yamauchi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato , Nobutoshi Aoki , Kazuya Ohuchi
发明人： Takashi Yamauchi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato , Nobutoshi Aoki , Kazuya Ohuchi
IPC分类号： H01L29/45
CPC分类号： H01L21/28537 , H01L21/265 , H01L21/28052 , H01L21/28518 , H01L29/41791 , H01L29/66143 , H01L29/66643 , H01L29/66795 , H01L29/7833 , H01L29/7839 , H01L29/785 , H01L29/872 , H01L2029/7858
摘要： It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.
摘要翻译： 可以降低硅化镍膜与硅之间界面处的界面电阻。 半导体制造方法包括：在硅衬底上形成杂质区域，杂质被引入杂质区域; 沉积Ni层以覆盖杂质区域; 通过退火将杂质区的表面改变成NiSi 2层; 在NiSi 2层上形成Ni层; 并通过退火对NiSi 2层进行硅化。
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公开(公告)号：US20070298558A1
公开(公告)日：2007-12-27
申请号：US11738687
申请日：2007-04-23
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/26513 , H01L21/28097 , H01L21/823814 , H01L21/823835 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device includes a first semiconductor region of first type conductivity with a channel region being formed therein, a gate electrode insulatively formed above the channel region, a layer of SixGe1-x (0
摘要翻译： 一种半导体器件包括：第一类型导电性的第一半导体区域，其中形成沟道区;绝缘地形成在沟道区上方的栅电极，一层Si x 1-x < / SUB>（0
层以具有范围为10 21至10 22原子/ cm 3的受控杂质浓度，以及上述含镍硅化物层 第二个半导体区域。 还公开了半导体器件的制造方法。 -
公开(公告)号：US20080179752A1
公开(公告)日：2008-07-31
申请号：US11898295
申请日：2007-09-11
IPC分类号： H01L29/78 , H01L21/336 , H01L23/48
CPC分类号： H01L29/66795 , H01L21/26513 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/47 , H01L29/66507 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66643 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film being sandwiched therebetween. Then, form a pair of heavily-doped p (p+) type diffusion layers in or on the substrate surface at both sides of the gate electrode to a concentration of 5×1019 atoms/cm3 or more and yet less than or equal to 1×1021 atoms/cm3. Next, silicidize the p+-type layers by reaction with a metal in the state that each layer is applied a compressive strain.
摘要翻译： 公开了具有应变通道区域的金属绝缘体半导体场效应晶体管（MISFET）。 还公开了一种制造具有低电阻结界面的半导体器件的方法。 该制造方法包括在硅衬底上形成栅电极的步骤，其间夹有栅绝缘膜。 然后，在栅极两侧的衬底表面中或其上形成一对重掺杂的p（p + SUP +）型扩散层，使其浓度达到5×10 19 原子/ cm 3以上且小于或等于1×10 21原子/ cm 3。 接下来，在各层施加压缩应变的状态下，通过与金属反应来硅化p + + +层。
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公开(公告)号：US08357580B2
公开(公告)日：2013-01-22
申请号：US12618402
申请日：2009-11-13
IPC分类号： H01L21/336 , H01L21/4763
CPC分类号： H01L21/28105 , H01L21/28097 , H01L21/32155 , H01L21/82385 , H01L29/66651 , H01L29/785
摘要： A semiconductor device includes a semiconductor substrate; a first gate insulation film formed on the semiconductor substrate; a second gate insulation film formed on the semiconductor substrate; a first gate electrode formed on the first gate insulation film and fully silicided; and a second gate electrode formed on the second gate insulation film and fully silicided, a gate length or a gate width of the second gate electrode being larger than that of the first gate electrode, and a thickness of the second gate electrode being smaller than that of the first gate electrode.
摘要翻译： 半导体器件包括半导体衬底; 形成在所述半导体基板上的第一栅极绝缘膜; 形成在所述半导体基板上的第二栅极绝缘膜; 形成在第一栅极绝缘膜上并完全硅化的第一栅电极; 以及形成在所述第二栅极绝缘膜上并完全硅化的第二栅电极，所述第二栅电极的栅极长度或栅极宽度大于所述第一栅电极的栅极长度或栅极宽度，并且所述第二栅电极的厚度小于所述第二栅电极的厚度 的第一栅电极。
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6.发明授权Method of forming a silicide layer while applying a compressive or tensile strain to impurity layers 失效在对杂质层施加压缩或拉伸应变的同时形成硅化物层的方法公开(公告)号：US07807538B2
公开(公告)日：2010-10-05
申请号：US11898295
申请日：2007-09-11
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L21/26513 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/47 , H01L29/66507 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66643 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film being sandwiched therebetween. Then, form a pair of heavily-doped p (p+) type diffusion layers in or on the substrate surface at both sides of the gate electrode to a concentration of 5×1019 atoms/cm3 or more and yet less than or equal to 1×1021 atoms/cm3. Next, silicidize the p+-type layers by reaction with a metal in the state that each layer is applied a compressive strain.
摘要翻译： 公开了具有应变通道区域的金属绝缘体半导体场效应晶体管（MISFET）。 还公开了一种制造具有低电阻结界面的半导体器件的方法。 该制造方法包括在硅衬底上形成栅电极的步骤，其间夹有栅绝缘膜。 然后，在栅电极两侧的基板表面中或其上形成一对重掺杂的p（p +）型扩散层，其浓度为5×1019原子/ cm3以上且小于等于1× 1021原子/ cm3。 接下来，在各层施加压缩应变的状态下，通过与金属反应来硅化p +型层。
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公开(公告)号：US07514753B2
公开(公告)日：2009-04-07
申请号：US11761288
申请日：2007-06-11
IPC分类号： H01L29/76
CPC分类号： H01L29/4908 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/4975 , H01L29/517 , H01L29/66643 , H01L29/785
摘要： A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a first gate electrode formed on the first gate insulator and including a compound of a metal M and a first group-IV elements Si1-a Gea (0≦a≦1), the p-type device including a p-channel region formed on the substrate, p-type source and drain regions formed opposite to each other interposing the p-channel region therebetween, a second gate insulator formed on the p-channel region, and a second gate electrode formed on the second gate insulator, and including a compound of the metal M and a second group-IV element Si1-c Gec (0≦c≦1, a≠c).
摘要翻译： 半导体器件包括形成在衬底上的n型和p型半导体器件，n型器件包括形成在衬底上的n沟道区，n型源极和漏极区彼此相对形成， 沟道区域，形成在n沟道区上的第一栅极绝缘体和形成在第一栅极绝缘体上的第一栅电极，并且包括金属M和第一族IV族元素Si1-a Gea（0≤...） a <= 1），所述p型器件包括形成在所述衬底上的p沟道区，形成在所述p沟道区之间的彼此相对形成的p型源极和漏极区，形成在所述p上的第二栅极绝缘体 以及形成在第二栅极绝缘体上的第二栅电极，并且包括金属M和第二IV族元素Si1-c Gec（0≤c≤1，a≤c）的化合物。
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8.发明申请公开(公告)号：US20090008726A1
公开(公告)日：2009-01-08
申请号：US12051947
申请日：2008-03-20
申请人： Takashi Yamauchi , Yoshifumi Nishi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato
发明人： Takashi Yamauchi , Yoshifumi Nishi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato
IPC分类号： H01L47/00 , H01L21/425
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823821 , H01L21/823835 , H01L21/823842 , H01L29/785
摘要： A method of manufacturing a semiconductor device reducing interface resistance of n-type and p-type MISFETs are provided. According to the method, a gate dielectric film and a gate electrode of the n-type MISFET are formed on a first semiconductor region, a gate dielectric film and a gate electrode of the p-type MISFET are formed on a second semiconductor region, an n-type diffusion layer is formed by ion implantation of As into the first semiconductor region, a first silicide layer is formed by first heat treatment after a first metal containing Ni is deposited on the n-type diffusion layer, the first silicide layer is made thicker by second heat treatment after a second metal containing Ni is deposited on the first silicide layer and second semiconductor region, and third heat treatment is provided after formation of a second silicide layer and ion implantation of B or Mg into the second silicide layer.
摘要翻译： 提供了制造半导体器件降低n型和p型MISFET的界面电阻的方法。 根据该方法，在第一半导体区域上形成栅极电介质膜和n型MISFET的栅电极，在第二半导体区域上形成p型MISFET的栅极电介质膜和栅电极， 通过将As离子注入第一半导体区域形成n型扩散层，在n型扩散层上沉积含有Ni的第一金属之后，通过第一热处理形成第一硅化物层，制作第一硅化物层 在第一硅化物层和第二半导体区域上沉积含有Ni的第二金属沉积第二热处理之后，在形成第二硅化物层和在第二硅化物层中离子注入B或Mg之后提供第三热处理。
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9.发明申请公开(公告)号：US20080308877A1
公开(公告)日：2008-12-18
申请号：US12193668
申请日：2008-08-18
IPC分类号： H01L27/08
CPC分类号： H01L21/28105 , H01L21/28097 , H01L21/32155 , H01L21/82385 , H01L29/66651 , H01L29/785
摘要： A semiconductor device includes a semiconductor substrate; a first gate insulation film formed on the semiconductor substrate; a second gate insulation film formed on the semiconductor substrate; a first gate electrode formed on the first gate insulation film and fully silicided; and a second gate electrode formed on the second gate insulation film and fully silicided, a gate length or a gate width of the second gate electrode being larger than that of the first gate electrode, and a thickness of the second gate electrode being smaller than that of the first gate electrode.
摘要翻译： 半导体器件包括半导体衬底; 形成在所述半导体基板上的第一栅极绝缘膜; 形成在所述半导体基板上的第二栅极绝缘膜; 形成在第一栅极绝缘膜上并完全硅化的第一栅电极; 以及形成在所述第二栅极绝缘膜上并完全硅化的第二栅电极，所述第二栅电极的栅极长度或栅极宽度大于所述第一栅电极的栅极长度或栅极宽度，并且所述第二栅电极的厚度小于所述第二栅电极的厚度 的第一栅电极。
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公开(公告)号：US20050127451A1
公开(公告)日：2005-06-16
申请号：US10997939
申请日：2004-11-29
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/76
CPC分类号： H01L29/4908 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/4975 , H01L29/517 , H01L29/66643 , H01L29/785
摘要： A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a first gate electrode formed on the first gate insulator and including a compound of a metal M and a first group-IV elements Si1−a Gea (0≦a≦1), the p-type device including a p-channel region formed on the substrate, p-type source and drain regions formed opposite to each other interposing the p-channel region therebetween, a second gate insulator formed on the p-channel region, and a second gate electrode formed on the second gate insulator, and including a compound of the metal M and a second group-IV element Si1−c Gec (0≦c≦1, a≠c).
摘要翻译： 半导体器件包括形成在衬底上的n型和p型半导体器件，n型器件包括形成在衬底上的n沟道区，n型源极和漏极区彼此相对形成， 沟道区域，形成在n沟道区上的第一栅极绝缘体和形成在第一栅极绝缘体上的第一栅电极，并且包括金属M和第一族IV元素Si 1-a的化合物， （0 <= a <= 1），p型器件包括形成在衬底上的p沟道区域，彼此相对形成的p型源极和漏极区域 在其间插入p沟道区域，形成在p沟道区域上的第二栅极绝缘体和形成在第二栅极绝缘体上的第二栅电极，并且包括金属M和第二IV族元素Si c）。
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