公开(公告)号：US06262924B1

公开(公告)日：2001-07-17

申请号：US09452168

申请日：1999-12-01

申请人： Yutaka Fukutani ,  Tomohiro Nakayama ,  Seizi Hirayama ,  Waichiro Fujieda ,  Arayama Youji ,  Atsushi Fujii ,  Yoshitaka Takahashi ,  Masanori Nagasawa ,  Masakazu Kimura ,  Tutomu Taniguti ,  Hiroyuki Fujimoto

发明人： Yutaka Fukutani ,  Tomohiro Nakayama ,  Seizi Hirayama ,  Waichiro Fujieda ,  Arayama Youji ,  Atsushi Fujii ,  Yoshitaka Takahashi ,  Masanori Nagasawa ,  Masakazu Kimura ,  Tutomu Taniguti ,  Hiroyuki Fujimoto

IPC分类号： G11C700

CPC分类号： G11C29/822 ,  G11C8/18 ,  G11C16/0441 ,  G11C16/10 ,  G11C17/12 ,  G11C29/80 ,  G11C29/83 ,  G11C29/846

摘要： A semiconductor memory device is provided with terminals for receiving a chip enable signal and an address signal, an internal circuit, and an internal control signal generating circuit for generating a predetermined internal control signal which makes an output timing of the semiconductor memory device same regardless of a level of the address signal when the chip enable signal undergoes a transition from an inactive level to an active level. The internal circuit is deactivated in response to the inactive level of the chip enable signal and is activated in response to the active level of the chip enable signal.

摘要翻译： 半导体存储器件设置有用于接收芯片使能信号和地址信号的端子，内部电路和内部控制信号产生电路，用于产生预定的内部控制信号，其使半导体存储器件的输出定时相同，而不管 当芯片使能信号经历从非活动电平转换到有效电平时的地址信号的电平。 内部电路响应于芯片使能信号的无效电平被去激活，并且响应于芯片使能信号的有效电平被激活。

公开(公告)号：US5831933A

公开(公告)日：1998-11-03

申请号：US847596

申请日：1997-04-25

申请人： Yutaka Fukutani ,  Tomohiro Nakayama ,  Seizi Hirayama ,  Waichiro Fujieda ,  Arayama Youji ,  Atsushi Fujii ,  Yoshitaka Takahashi ,  Masanori Nagasawa ,  Masakazu Kimura ,  Tutomu Taniguti ,  Hiroyuki Fujimoto

发明人： Yutaka Fukutani ,  Tomohiro Nakayama ,  Seizi Hirayama ,  Waichiro Fujieda ,  Arayama Youji ,  Atsushi Fujii ,  Yoshitaka Takahashi ,  Masanori Nagasawa ,  Masakazu Kimura ,  Tutomu Taniguti ,  Hiroyuki Fujimoto

IPC分类号： G11C8/18 ,  G11C16/04 ,  G11C17/12 ,  G11C29/00 ,  G11C8/00

CPC分类号： G11C29/80 ,  G11C16/0441 ,  G11C17/12 ,  G11C29/822 ,  G11C29/83 ,  G11C29/846 ,  G11C8/18

摘要： A semiconductor memory device is provided with terminals for receiving a chip enable signal and an address signal, an internal circuit, and an internal control signal generating circuit for generating a predetermined internal control signal which makes an output timing of the semiconductor memory device same regardless of a level of the address signal when the chip enable signal undergoes a transition from an inactive level to an active level. The internal circuit is deactivated in response to the inactive level of the chip enable signal and is activated in response to the active level of the chip enable signal.

公开(公告)号：US6026052A

公开(公告)日：2000-02-15

申请号：US107408

申请日：1998-06-30

申请人： Yutaka Fukutani ,  Tomohiro Nakayama ,  Seizi Hirayama ,  Waichiro Fujieda ,  Arayama Youji ,  Atsushi Fujii ,  Yoshitaka Takahashi ,  Masanori Nagasawa ,  Masakazu Kimura ,  Tutomu Taniguti ,  Hiroyuki Fujimoto

发明人： Yutaka Fukutani ,  Tomohiro Nakayama ,  Seizi Hirayama ,  Waichiro Fujieda ,  Arayama Youji ,  Atsushi Fujii ,  Yoshitaka Takahashi ,  Masanori Nagasawa ,  Masakazu Kimura ,  Tutomu Taniguti ,  Hiroyuki Fujimoto

IPC分类号： G11C8/18 ,  G11C16/04 ,  G11C16/10 ,  G11C17/12 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/822 ,  G11C16/0441 ,  G11C16/10 ,  G11C17/12 ,  G11C29/80 ,  G11C29/83 ,  G11C29/846 ,  G11C8/18

摘要： A semiconductor memory device is provided with terminals for receiving a chip enable signal and an address signal, an internal circuit, and an internal control signal generating circuit for generating a predetermined internal control signal which makes an output timing of the semiconductor memory device same regardless of a level of the address signal when the chip enable signal undergoes a transition from an inactive level to an active level. The internal circuit is deactivated in response to the inactive level of the chip enable signal and is activated in response to the active level of the chip enable signal.

摘要翻译： 半导体存储器件设置有用于接收芯片使能信号和地址信号的端子，内部电路和内部控制信号产生电路，用于产生预定的内部控制信号，其使半导体存储器件的输出定时相同，而不管 当芯片使能信号经历从非活动电平转换到有效电平时的地址信号的电平。 内部电路响应于芯片使能信号的无效电平被去激活，并且响应于芯片使能信号的有效电平被激活。

公开(公告)号：US5661694A

公开(公告)日：1997-08-26

申请号：US237303

申请日：1994-05-03

申请人： Yutaka Fukutani ,  Tomohiro Nakayama ,  Seizi Hirayama ,  Waichiro Fujieda ,  Arayama Youji ,  Atsushi Fujii ,  Yoshitaka Takahashi ,  Masanori Nagasawa ,  Masakazu Kimura ,  Tutomu Taniguti ,  Hiroyuki Fujimoto

发明人： Yutaka Fukutani ,  Tomohiro Nakayama ,  Seizi Hirayama ,  Waichiro Fujieda ,  Arayama Youji ,  Atsushi Fujii ,  Yoshitaka Takahashi ,  Masanori Nagasawa ,  Masakazu Kimura ,  Tutomu Taniguti ,  Hiroyuki Fujimoto

IPC分类号： G11C8/18 ,  G11C16/04 ,  G11C17/12 ,  G11C29/00 ,  G11C8/00

CPC分类号： G11C29/80 ,  G11C16/0441 ,  G11C17/12 ,  G11C29/822 ,  G11C29/83 ,  G11C29/846 ,  G11C8/18

摘要： A semiconductor memory device is provided with terminals for receiving a chip enable signal and an address signal, an internal circuit, and an internal control signal generating circuit for generating a predetermined internal control signal which makes an output timing of the semiconductor memory device same regardless of a level of the address signal when the chip enable signal undergoes a transition from an inactive level to an active level. The internal circuit is deactivated in response to the inactive level of the chip enable signal and is activated in response to the active level of the chip enable signal.

摘要翻译： 半导体存储器件设置有用于接收芯片使能信号和地址信号的端子，内部电路和内部控制信号产生电路，用于产生预定的内部控制信号，其使半导体存储器件的输出定时相同，而不管 当芯片使能信号经历从非活动电平转换到有效电平时的地址信号的电平。 内部电路响应于芯片使能信号的无效电平被去激活，并且响应于芯片使能信号的有效电平被激活。

公开(公告)号：US5563841A

公开(公告)日：1996-10-08

申请号：US503610

申请日：1995-07-18

申请人： Atsushi Fujii ,  Yoshitaka Takahashi

发明人： Atsushi Fujii ,  Yoshitaka Takahashi

IPC分类号： G11C17/18 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C29/78 ,  G11C29/781

摘要： A semiconductor memory device includes a memory cell array divided into a first memory cell array for an upper address of an input address and a second memory cell array for a lower address of the input address, a redundant cell array storing correction data, a first sense amplifier provided with respect to the first memory cell array, a first column decoder provided with respect to the first memory cell array, a second sense amplifier provided with respect to the second memory cell array, and a second column decoder provided with respect to the second memory cell array. The second sense amplifier and the second column decoder are non-selected when an access is made to the first memory cell array by the input address. The non-selected second sense amplifier and second column decoder operate as a sense amplifier and a column decoder provided with respect to the redundant cell array to thereby output the correction data from the upper address of the redundant cell array.

摘要翻译： 半导体存储器件包括：存储单元阵列，被划分为用于输入地址的高地址的第一存储单元阵列和用于输入地址的较低地址的第二存储单元阵列;存储校正数据的冗余单元阵列;第一感测 相对于第一存储单元阵列提供的放大器，相对于第一存储单元阵列提供的第一列解码器，相对于第二存储单元阵列提供的第二读出放大器，以及相对于第二存储单元阵列提供的第二列解码器 存储单元阵列。 当通过输入地址访问第一存储器单元阵列时，第二读出放大器和第二列解码器是未选择的。 未选择的第二读出放大器和第二列解码器用作相对于冗余单元阵列提供的读出放大器和列解码器，从而从冗余单元阵列的上部地址输出校正数据。

公开(公告)号：US20120121291A1

公开(公告)日：2012-05-17

申请号：US13384149

申请日：2010-09-03

申请人： Haruyuki Tsuji ,  Atsushi Fujii ,  Hideaki Matsuoka

发明人： Haruyuki Tsuji ,  Atsushi Fujii ,  Hideaki Matsuoka

IPC分类号： G03G21/18 ,  G03G15/00

CPC分类号： G03G5/144 ,  G03G5/102 ,  G03G5/142

摘要： An electrophotographic photosensitive member having a specific conductive layer and promising less variation in light-area potential and residual potential in reproducing images repeatedly, and a process cartridge and an electrophotographic apparatus which have such an electrophotographic photosensitive member are provided. Where a test in which a voltage of −1.0 kV having only a DC voltage component is continuously applied to the conductive layer for 1 hour is conducted, the conductive layer has volume resistivity satisfying the following mathematical expressions (1) and (2), as values before and after the test: −2.00≦(log|ρ2|−log|ρ1|)≦2.00  (1), and 1.0×108≦ρ1≦2.0×1013  (2), where, in the expressions (1) and (2), ρ1 is volume resistivity (Ω·cm) of the conductive layer as measured before the test and ρ2 is volume resistivity (Ω·cm) of the conductive layer as measured after the test.

摘要翻译： 提供具有特定导电层的电子照相感光构件，并且重复地再现图像中的光区电位和剩余电位的变化较小，以及具有这种电子照相感光构件的处理盒和电子照相设备。 在进行1小时的连续施加直流电压成分的-1.0kV的电压的试验中，导电层的体积电阻率满足下述数学式（1）和（2），如 测试前后的值：-2.00＆nlE;（log |＆rgr; 2 | -log |＆rgr; 1 |）＆nlE; 2.00（1）和1.0×108＆nlE;＆rgr; 1＆nlE; 2.0×1013（2） 在表达式（1）和（2）中，＆rgr; 1是测试前测量的导电层的体积电阻率（＆OHgr;·cm），2是导电层的体积电阻率（＆OHgr·cm） 在测试后测量。

公开(公告)号：US07913494B2

公开(公告)日：2011-03-29

申请号：US11683614

申请日：2007-03-08

申请人： Nagayoshi Hiromitsu ,  Jun Hosoi ,  Atsushi Fujii ,  Tsukasa Saitou ,  Dirk Riechelmann ,  Junichi Sato

发明人： Nagayoshi Hiromitsu ,  Jun Hosoi ,  Atsushi Fujii ,  Tsukasa Saitou ,  Dirk Riechelmann ,  Junichi Sato

IPC分类号： F02C1/00 ,  F02G3/00

CPC分类号： F23C7/002 ,  F23D2900/14021 ,  F23R3/12 ,  F23R3/286

摘要： A burner 1 for combustion chamber is provided with a cylindrical mixing portion 3 that mixes air for combustion (oxidizing agent) and fuel in the interior thereof and has one end 3a that opens to a combustion portion 2; a spray nozzle (fuel spraying portion) 5 that sprays fuel in the mixing portion 3, being disposed on another end 3b of the mixing portion 3; first blowing ports 6 that introduce the air for combustion to the mixing portion 3 to form a swirling flow with the fuel, being disposed to open to the inner wall of the mixing portion 3; and second blowing ports 7 that additionally introduce the air for combustion to the mixing portion 3, opening in a direction different from the first blowing ports 6 and being disposed further to the other end 3b side of the mixing portion 3 than the swirling flow. The burner for combustion chamber and combustion method of the present invention can shorten the flame length in the central axial direction by improving the combustion efficiency even during low loading and shorten the overall length of the burner for combustion chamber in the central axial direction.

摘要翻译： 用于燃烧室的燃烧器1设置有将燃烧空气（氧化剂）和其内部的燃料混合的圆柱形混合部分3，并且具有通向燃烧部分2的一端3a; 在混合部3中喷射燃料的喷嘴（燃料喷射部）5，配置在混合部3的另一端3b上; 第一吹送口6，其将用于燃烧的空气引入混合部分3以与燃料形成旋流，设置成向混合部分3的内壁开口; 以及向混合部3另外引入用于燃烧的空气的第二吹出口7，其与第一吹出口6不同的方向开口，并且比旋转流更加配置在混合部3的另一端3b侧。 本发明的燃烧室燃烧器和燃烧方法可以通过即使在低负荷期间提高燃烧效率也可缩短中心轴向的火焰长度，缩短燃烧室燃烧室在中心轴线方向上的总长度。

公开(公告)号：US07452644B2

公开(公告)日：2008-11-18

申请号：US11358204

申请日：2006-02-22

申请人： Masato Tanaka ,  Masataka Kawahara ,  Atsushi Fujii ,  Yuka Ishizuka

发明人： Masato Tanaka ,  Masataka Kawahara ,  Atsushi Fujii ,  Yuka Ishizuka

IPC分类号： G03G5/047

CPC分类号： G03G5/144 ,  G03G5/0517 ,  G03G5/0542 ,  G03G5/0571 ,  G03G5/0601 ,  G03G5/0609 ,  G03G5/0679 ,  G03G5/0696 ,  G03G5/0698 ,  G03G5/142

摘要： An electrophotographic photosensitive member capable of outputting an image in which a defect such as a ghost is suppressed even in a high-temperature-and-high-humidity environment, and in which a defect such as a change in density due to an abrupt change in light-area potential at an initial stage or a ghost due to long-term durable use is suppressed even in a low-humidity environment; and a process cartridge and an electrophotographic apparatus each having the electrophotographic photosensitive member; are provided. The electrophotographic photosensitive member has a layer which comprises a compound having a specific structure between a support and a charge-generating layer.

摘要翻译： 能够输出即使在高温高湿环境下也能抑制诸如重影等缺陷的图像的电子照相感光构件，其中由于突然变化引起的密度变化等缺陷 甚至在低湿度环境下也抑制了由于长期耐久使用而导致的初始阶段或重影的光区电位; 以及各自具有电照相感光构件的处理盒和电子照相设备; 被提供。 电子照相感光构件具有包含在载体和电荷产生层之间具有特定结构的化合物的层。

公开(公告)号：US20080159041A1

公开(公告)日：2008-07-03

申请号：US12005389

申请日：2007-12-27

申请人： Masaki Okuda ,  Atsushi Fujii

发明人： Masaki Okuda ,  Atsushi Fujii

IPC分类号： G11C7/22 ,  G11C29/00

CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C11/406 ,  G11C29/14 ,  G11C29/50012 ,  G11C2211/4061

摘要： A semiconductor memory has a memory cell array having dynamic memory cells. An access control circuit accesses the memory cells in response to an access command which is supplied externally. A refresh control circuit generates, during a test mode, a test refresh request signal in synchronization with the access command so as to execute a refresh operation of the memory cells when a refresh mask signal is at an invalid level. Also, the refresh control circuit prohibits generation of the test refresh request signal when the refresh mask signal is at a valid level. The test refresh request signal is generated or prohibited from being generated according to the level of the refresh mask signal. Thus, only a refresh operation needed for a test can be executed, and hence test efficiency can be improved.

摘要翻译： 半导体存储器具有具有动态存储单元的存储单元阵列。 访问控制电路响应于外部提供的访问命令来访问存储器单元。 刷新控制电路在测试模式期间与访问命令同步地生成测试刷新请求信号，以便当刷新屏蔽信号处于无效级时执行存储器单元的刷新操作。 此外，当刷新屏蔽信号处于有效电平时，刷新控制电路禁止产生测试刷新请求信号。 生成或禁止根据刷新屏蔽信号的电平生成测试刷新请求信号。 因此，可以仅执行测试所需的刷新操作，因此可以提高测试效率。

公开(公告)号：US07097950B2

公开(公告)日：2006-08-29

申请号：US11151309

申请日：2005-06-14

申请人： Masato Tanaka ,  Masataka Kawahara ,  Atsushi Fujii ,  Yuka Ishizuka

发明人： Masato Tanaka ,  Masataka Kawahara ,  Atsushi Fujii ,  Yuka Ishizuka

IPC分类号： G03G5/047

CPC分类号： G03G5/144 ,  G03G5/0517 ,  G03G5/0542 ,  G03G5/0571 ,  G03G5/0601 ,  G03G5/0609 ,  G03G5/0679 ,  G03G5/0696 ,  G03G5/0698 ,  G03G5/142

摘要： An electrophotographic photosensitive member capable of outputting an image in which a defect such as a ghost is suppressed even in a high-temperature-and-high-humidity environment, and in which a defect such as a change in density due to an abrupt change in light-area potential at an initial stage or a ghost due to long-term durable use is suppressed even in a low-humidity environment; and a process cartridge and an electrophotographic apparatus each having the electrophotographic photosensitive member; are provided. The electrophotographic photosensitive member has a layer which comprises a compound having a specific structure between a support and a charge-generating layer.

摘要翻译： 能够输出即使在高温高湿环境下也能抑制诸如重影等缺陷的图像的电子照相感光构件，其中由于突然变化引起的密度变化等缺陷 甚至在低湿度环境下也抑制了由于长期耐久使用而导致的初始阶段或重影的光区电位; 并且提供各自具有电子照相感光构件的处理盒和电子照相设备。 电子照相感光构件具有包含在载体和电荷产生层之间具有特定结构的化合物的层。